I was unaware that Y had to remain 0 as that's not in any comments
Apologies, Ray... If you look again you'll see I edited my post. This was promptly after I submitted the erroneous content, but unfortunately you'd already seen it, it seems.

To be clear, Y does not have to remain equal to zero ...

Just let Claude do your taxes! What could go wrong?

-- Jeff

Hello, v6ops, and (belated) welcome. :)

Q1. I had to add an extra line to BRAN: to get that working, because the branch offsets weren't being calculated correctly. Firstly, allow me to suggest you use the Code tags for better clarity (see below).

As for the incorrect the branch offsets, adding ...

Thank you for writing about your adventures with Claude! It's been interesting following along. I too am grateful for you sharing your experience, Martin.

In many cases Claude's performance was perplexing or outright disappointing. But the impression I take away has some surprises of a positive ...

Claude likes BDD's technique of pointing the direct page register to the stack
FWIW, I don't think BDD claims to have originated this idea. But I daresay it has been independently dreamed up by various different folks... beginning with the '816 designers! (and it's they who deserve the most credit ...

A 16V8 could be made to do what you want, and with low prop time. Agree about the low prop time, but a 16V8 has 8 macrocells, each with only 1 bit of storage. Thus it's incapable of replacing a '670, which has sixteen bits of storage.

(I see John West has just posted, including that same point ...

Oooo! -- the '670!

It's a delightful little nugget of Solution, apt for a surprising variety of Problems! :mrgreen: And this includes memory mapping arrangements. (I wrote about the '670 here .)

It seems the write side of the chip is something like a transparent latch that latches on the rising ...

[...]
To me, that's what dissecting chips feels like.
Plus that "Indiana Jones factor", when you always expect to bump into traps and man eating bugs behind the next corner. ;)
To quote a former coworker: " It is fun, but not everybody can take that much fun ."
Dieter, you crack me up! And it's ...

Interesting proposal, Neil! And lots to think about. Here are some points that come to mind.

the DMA can run at multiples of the system clock I agree this is doable, but -- realistically -- is it something you'd actually want to undertake? It implies two different clocks, with part of the system ...

The '521 is the same thing, and the CD74FCT521CT maxes out at 4.5ns.
Same functionality, yes, and single-digit prop time. However, inputs and outputs are TTL, even when V CC is 5 volts. I can’t see how that device could be successfully integrated into an all-CMOS system running on 5 volts.
I too ...

During memory read/write clock cycles the chip enable line goes low and high within the clock cycle which works fine for RAM and ROM but a read/write VIA clock cycle doesn't complete until I send another clock cycle of some sort.
If you mean the VIA's chip enable line goes low and high within the ...

Note that you'll need some circuitry to start and stop the clock. [...]
In the post where I initially talked about this idea , there's a screenshot of that circuit (Fig. 8 ) for the Rockwell chip. OK -- looks good.

Yes, but what is it that provides the cue for the clock to restart?
The ESP32 on ...

Yes, it's very nice!

... and presently on the front page of Hacker News! (posted 5 hours ago)

Here is a link to the comments.

-- Jeff

I was counting on it to resume when the clock is restarted. Is that not how it works?
Yes, but what is it that provides the cue for the clock to restart? (Is it input from the human, for example?)

Note that you'll need some circuitry to start and stop the clock. And, to do so cleanly (ie, without ...

I could use some of the other gates as inverters in the clock circuit. :idea:
Yup. But instead (or as well) it's good to be aware of the following. These little beasties can also solve problems having to do with speed .

-- Jeff

Tiny, superfast gates rival programmable logic

Logic gates are ...