Arlet core register timing
Posted: Thu Mar 05, 2026 1:01 pm
Hi,
I am trying to understand some aspect with the Arlet's 6502 core that may have been discussed before. Anyway its related to how the load_reg is set and the use of it to set write_register.
The thing is that load_reg is assigned with a non-blocking assignment (so it can be delayed). Now that is usually fine, but if the next instruction is a write register instruction, write_register uses load_reg.
This is probably also fine, but in some instances the load_reg could become delayed. For example with LDA $1234,X, which would, if the next instruction is a STA then cause the write_register to fire AXYS[regsel].
As said, this is usually not a problem, but if timing gets constrained I am thinking that it may give rise to some problematic register update. Or maybe I am just being paranoid. I was originally thinking around the RDY assertion when I started thinking of this.
Anyway, could it be an idea to gate the write_register?
I am trying to understand some aspect with the Arlet's 6502 core that may have been discussed before. Anyway its related to how the load_reg is set and the use of it to set write_register.
The thing is that load_reg is assigned with a non-blocking assignment (so it can be delayed). Now that is usually fine, but if the next instruction is a write register instruction, write_register uses load_reg.
This is probably also fine, but in some instances the load_reg could become delayed. For example with LDA $1234,X, which would, if the next instruction is a STA then cause the write_register to fire AXYS[regsel].
As said, this is usually not a problem, but if timing gets constrained I am thinking that it may give rise to some problematic register update. Or maybe I am just being paranoid. I was originally thinking around the RDY assertion when I started thinking of this.
Anyway, could it be an idea to gate the write_register?