6502.org

Having done a whole 6502 system based off Ben Eater stuff, I am not starting on a 65C816 system.

My aim is to have 2 X 6522, 1 serial, 16K or 32K ROM, all other memory as RAM using 2 or more AS6C4008 chips.
The project will be on a PCB, all through hole, aim is to get 4Mhz.

Trying to get my head around address decoding for 1M or 2M or RAM.

Several people seem to use a GAL or other programmed logic.
Other people seem to use standard 74XX gates.

What's a good way to get my head around doing it as 74XX logic?
Is there some kind of tool I can use to help?

Welcome!

I had a look, and perhaps this previous topic will be helpful:
65c816 address decoding help

FWIW: My project is all through hole, 2-sided board and runs at 16MHz. I use 2 GALs. It only has 512KB of RAM though - I thought long and hard about how much RAM to give it, but at the end of the day what was I going to use it for? Academically, I could write an application that used it all, but even the BCPL compiler I use on it only needs 48KB of RAM...

Big games and graphics excepted, of-course!

-Gordon

First off, welcome!
Just as one of the first things to be established when designing and building a house is the floor plan, in computer design, one of the first things to be established is the memory map.  I suggest you publish a memory map, which among other things, will help you visualize how decoding will have to work.  Getting into hardware aspects before defining the memory map and other architectural considerations is akin to shopping for bricks before designing the house with which they are to be used.
Memory map first, my friend!  You need to balance wants with needs, which starts with defining what those wants and needs are.  Right now, you are shopping for bricks, but haven’t designed the house.

If you are truly going for that much RAM, you need to look beyond the AS6C4008 to something with much higher density.  Otherwise, your glue logic will become unwieldy.  Also, you need to consider operating voltage.  As far as I know, the largest static RAM available in 5 volts is 512 KB.  Larger SRAMs seem to use 3.3 volts
I’ve done considerable analysis on this, and have concluded that once a system gets beyond 128 KB, programmable logic is the better choice—fewer discrete devices are required and timing problems arising from propagation delay are considerably lessened.  A distinct advantage of a GAL working as combinatorial logic is the constant prop time regardless of effective address, something that is difficult to achieve with cascaded discrete logic.

For a system with up to 512 KB in a single SRAM, use of a GAL as glue logic, e.g., an Atmel ATF22V10, is sufficient—Gordon, who posted above, built his 16 MHz 65C816 system around two GALs and supports 512 KB.  Beyond 512 KB, a CPLD is the better choice, due to its considerably larger logic fabric and greater number of I/O pins.  If your machine has more than 512 KB, you will likely need multiple SRAM chip-select signals; the 22V10 GAL only has 10 pins that may be defined as outputs, versus 32 pins on an Atmel ATF1504 CPLD.

You will also have to consider bank bits latching, as the 65C816 multiplexes A16-A23 onto the data bus during the low phase of Ø2.  Latching is a timing-critical operation, which demands the use of very fast logic if the 816 is to be clocked at its maximum.

However, until you have defined your machine’s architecture, looking at hardware specifics will be premature.
See above!