6502.org

I did my first PCB for my 6502 setup, and surprisingly it is all working as expected. Now I want to see if I can do it "properly". I have been reading a lot on the forum and checked out a lot of linked web sources. Just to be clear, my setup will initially run at 4MHz, but I might crank it up to 8MHz later on. My PCBs are 4-layer ones (stacked signal-ground-power-signal with most components on the top layer), and for now I use through-hole for the chips (I am not yet confident enough to use SMT versions of the chips), and all resistors and capacitors are surface-mount. I use KiCad and do all the trace routing by hand (no auto-routing).

A lot of the info in designing PCBs give various pieces of advise, and pretty much all of them make sense. However, in some cases I run into conflicts. For instance, when laying out signal traces on the PCB, it is best to make sure it has a ground return that closely follows the signal trace. Also, connections should ideally be as short as possible. When using the defaults for KiCad, laying out a PCB ends up like this:In this picture, the green area shows the copper deposited for the ground layer. Here you can see that the clearance for the through-hole pins causes the ground layer to show a gap for each line of pins. When routing a signal line in between the pins, the ground return then has to go around the rows of pins. What would you do here? Adjust the clearances so the through-holes punch smaller holes in the ground layer (thus allowing the ground return to flow in between the pins), re-route connections to go around the pin rows (thus making them substantially longer and possibly causing a "traffic jam" of traces outside the pin rows), or leave the PCB as-is (so the ground return takes a detour around the pin rows)? To me, changing the parameters of the board so the holes in the ground layer would be smaller makes the most sense, but it might run afoul of the capabilities of the PCB manufacturer (I've used both pcbway and jlcpcb).

Another question is about which resistors and caps to use - not the values etc, but whether to use through-hole or SMT. For these "analog" components I used SMT because it is easier to lay out (I can easily put bypass caps in between the pin rows etc), but I don't really know if there are advantages or disadvantages to use either type.

I am fully aware that especially the routing questions are likely of little consequence for the speeds I am working with, but I would like to get into the habit of doing "proper" PCB layouts (if that makes sense).

-Niek.

Hmm. As the red layer can route between pins 22 and 23 without danger of shorting against the rings, it seems to me that the green layer should be able to do the same. In other words, I'd expect the spacing rules to allow for a smaller gap around the pin surrounds. I'd be interested to hear otherwise.

IMHO the ground return goes via GND pin of such chip (which is usually on one end), so avoiding the trap around pins line.

Thanks all. I haven't had time to poke at the PCB layout some more (struggling with after-surgery complications), will chime back in this week hopefully.

-Niek.

I'm not sure what you mean here; but if there's a signal line that runs through the middle of an IC, between pins, you want its return current to be able to run directly under it, not having to go down around the "southern tip of Africa" so to speak.  When the return current in the ground plane can't take the path of the signal line, you open up a gap, a space, that must be charged up with this electromagnetic field, increasing inductance, and trying to collapse on other traces that are closer, causing unwanted coupling between signal lines.  If edge rates are slow (like 74HC or slower), it probably won't hurt anything; but as you get into faster stuff (like 74AC and above), it may sometimes cause trouble.