6502.org

Having become bored with scrolling through several hundred pages of PDF to find information - most frequently, which addressing modes are available, and which flags are affected - I put the information together in a convenient table.

[File corrected: latest version is below]

Opcodes in black are NMOS 6502 original instructions; those in red are later CMOS versions. The flag columns indicate merely that a particular flag _may_ be changed by a given instruction, not the value to which it changes.

Italics indicate the Rockwell bit setting/testing instructions, which in Western Design's 2007 "Programming the 65816 Including the 6502, 65C02, and 65802" are relegated to an appendix on the grounds that they clash with some 65816 instructions. However, they are present in the opcode table in WDC's 2024 W65C02S datasheet.

The Progamming book also indicates that WAI and STP instructions are not included in the 65c02, but again, they are there in the 2024 datasheet.

Please let me know if this is incorrect anywhere. I wanted something to remind me of the new instructions and operating modes on the 65c02 as that's what's currently available!

Neil

edit: corrected CLC opcode!
edit: this table corrected further below

I'm a little puzzled by how the rmb/smb/etc. instructions in the table should be interpreted.

Otherwise it's very easy to read. Thank you.

Regarding BRK, you might want to footnote that the b flag exists only in the copy of the status register (SR) that is pushed when the instruction is executed.  A naive programmer might otherwise try to PHP - PLA - BIT #%00010000 to examine SR to differentiate between and IRQ and a BRK instruction.

Also, in your chart, you indicate that PLP and RTI affect all SR flags.  That is not quite correct; the b flag and bit 5 are never affected by those instructions—bit 5 is always set.  Note that the Eyes & Lichty description of PLP incorrectly shows b as being affected by the instruction.  On the other hand, their description of RTI correctly shows that b is unaffected.

TRB and TSB affect z, as those instructions perform a logical AND between the accumulator and the affected memory location.  The logical AND occurs before any bits are cleared (TRB) or set (TSB).

PLX and PLY affect n and z, which is not noted in your chart.

ADC affects c, n, v and z, but is only showing that it affects n and z.
The Eyes & Lichty manual was published in 1986 and hence predates the time when WDC officially incorporated the Rockwell extensions in the 65C02 ISA.  At the time the manual was published, only the Rockwell rendition of the 65C02 had the extensions.  Use of the extensions makes 65C02 code non-portable to the 65C816 and 65C802 when these MPUs are operated in emulation mode, which was likely a consideration when Eyes and Lichty were composing their manual.
Those two didn’t appear in the C02’s ISA until well after the Eyes & Lichty manual had been published.  The earliest C02 data sheet I have that mentions STP and WAI is from February 1990, which curiously predates the conversion of the C02 to a static core.
What?  You mean to tell me you don’t have all that stuff memorized? 
Here’s an example of usage of SMB (set memory bit), as coded in the Kowalski assembler:


Syntax in some assemblers appends the bit number to the mnemonic, which is non-standard when considered against the original 6502 assembly language definition.

The Rockwell extensions are of somewhat limited value, as their only addressing mode is zero page.  At the time of their development, Rockwell’s main interest in the 65C02 was in embedded applications, especially modems, in which the UART’s registers were mapped into zero page.  BBR, BBS, RMB and SMB were created specifically to interact with the registers.  Back when I did 65C02 development, I never found a use for them, but did make extensive use of TRB and TSB.  Unlike the extensions, those two are not bound to zero page, can manipulate multiple bits with one instruction, and are portable to the 65C816.

Thanks for the corrections, BDD.

I missed the flag effects on the new instructions, oops! Should be added now, see below.

PLP and RTI flag effects were taken from Zaks - could be a misprint there. Changed to include your correction.

WAI and STP italics removed as they're now canonical, but I'm leaving 'em in for RMB/SMB Like you, I've never used them.

@6502inside: BBR and friends use the number of the bit in question as bits 4-6 of the instruction, so e.g. smb0 is $87, smb1 is $97 etc (or smb #0,zp smb #1,zp in BDD's example syntax)

I was looking only for a quick reference, so I haven't gone into any details about how the instructions work, just how you can use them. Nor have I considered the sixteen bit parts, none of which I've ever used.
Neil

Most of what you want is here: https://www.pagetable.com/c64ref/6502/?cpu=65c02s&tab=4

Neil produced his chart so he could use it off-line.

I allow them an alternative syntax of: RES n,zp and SET n,zp to clarify what they are doing. So, for example: SET 7,&FF.