6502.org

Way back in 2016 (viewtopic.php?f=10&t=4224), Dave [hoglet] and Ed presented their 65C02 extensions to Arlet's 6502 core. In that thread, Dave mentions an issue with using RDY to insert a wait state and suggested a fix. But in the 65C02 code that's on GitHub (https://github.com/hoglet67/verilog-6502), this fix is not implemented. Instead there's a note that says:
And indeed the DIHOLD logic is commented and DIMUX always gets set to DI.

Does anyone know why the fix wasn't implemented, and what the consequence of the DIHOLD logic being commented out is? It's been this way for years so I'm guessing that the core is working fine without the fix. But is there is anything I should look out for? Or should I just apply the suggested fix?

Gosh, this does seem like a long time ago! I can only assume I was being cautious. As Arlet was already aware of the issue, I was hoping it would get addressed upstream by him in due course. Which I think he did a few days later here.

I find RDY logic is quite hard to test comprehensively. Though I guess you could just randomly assert RDY (and provide incorrect data when RDY is de-asserted). The use of RDY in the Matchbox Co Processor is quite limited. I think it's dangerous to generalize too much from that use case. Arlet's fix looks better to me than just commenting out the code!

What's your use case for RDY?

Are you using the 6502 or 65C02 version?

Looking at Atlet's fix in more detail: This bit of logic ensures the DIMUX signal has the most recent valid DI sample. The rest of the core then uses DIMUX in place of DI. This guarantees that decisions are never made based on invalid (RDY=0) values of DI.

I would suggest using that fragment in the 65c02 core.

By the way, Artlet later developed his own microcoded 65C02 implementation:
https://github.com/Arlet/verilog-65C02-microcode

There is also the AlanD core, which the one I now use in my Acorn FPGA projects, as it's cycle accurate (*):
https://github.com/hoglet67/AtomBusMon/ ... R65Cx2.vhd

(*) well almost - I recently discovered RTI takes 7 cycles rather than 6. There are a few more cases that came to light now we have a comprehensive cycle accuracy test suite, see here for the gory details.

Thanks for your reply! It didn't occur to me to check if anyone had fixed it in the original 6502 core, which I have used before.

I was aware of Arlet's own 65C02 core even before I discovered your improvements to his original one, like years ago, but at the time I didn't know Verilog very well and the original 6502 core seemed simpler so I used that. It worked on the first try so I'm partial to it.

I was considering one of the other cores that replicates the original 6502 cycle timing and requires either asynchronous memory or wait states. I figured I'd use asynchronous distributed RAM for zero page and stack and then use RDY to insert a wait state when accessing the rest of the address space in block RAM. With the Arlet core I don't need RDY so much, but I saw the comment about the RDY issue and was wondering why commenting out DIHOLD was possible without any apparent negative consequences.

My project is a FPGA-based retrocomputer. I want to try rolling my own sound and graphics, since those were the distinguishing features of early 6502 machines.

I sent you a pull request: https://github.com/hoglet67/verilog-6502/pull/1

Thanks, merged.