6502.org

As previously mention on this thread I'm looking at a hypothetical "fast BBC micro" design. A key criterion is to be able to run the system VIA at a steady 1 MHz clock, because it's used as the system timer.

More by luck than judgment I've come up with the attached design, which appears to work in the "Circuit" logic emulator, but which I have yet to commit to real hardware, as I don't have the chips to hand. In part this is inspired by George's thread (especially the generation of a slow IOCS line), but also by Youtuber Adrien Kohlbecker whose 65816 design gave me the "A-ha" moment for the cascaded flip flops.

The core clock speed is 8 MHz, with some IO devices at page &FE ("Sheila") driven at 2 MHz while others (the "Fred" and "Jim" pages at pages &FC and &FD) and other parts of page &FE are driven at 1 MHz. The test address generator for now doesn't worry about splitting page &FE into 1 MHz and 2 MHz.

The IOCLK defaults to running at 1 MHz, but jumps to 2 MHz briefly whenever a relevant device is selected. A simple MUX toggles the IOCLK speed to 2MHz if required based on the selected address.

If a slow IO address is selected (IOREQ) then at the next rising edge of CLK8 a D-type latch stores IOREQ to indicate the start of a long cycle, and this latched IOREQ is OR'd with CLK8 to generate the stretched PHI2. NB: this does mean that the clock stretcher currently does expect the address bus to be settled by the rising edge of the (pre-stretched) 8 MHz clock.

Subsequently the circuit waits for the next falling edge of IOCLK, and this marks the start of the usable clock cycle (~IOCS), stored by the first J/K flip flop. The next falling edge after that is captured by the second J/K flip flop and that is used to reset the D-type latch to start the cycle again.

The test circuit generates page addresses &F0 - &FF, but with an 4:1 duty cycle of fast unstretched addresses interleaved between the slow cycles. I've tested it (in Circuit) without fast cycles between the three slow cycles and it still works.

I'd love feedback, especially if someone manages to built this before AliExpress get the extra chips I need to me! I'd be slightly amazed if it does actually work for real. Sequential logic was never by strong point...

Ray

Here's the "Circuit" emulation file for this.

In the good old days there were a few accelerator boards for the Beeb - I had a 4Mhz one and it worked really well. They worked by removing the 6502 and replacing it with a board that had a faster 65C02 plus some glue logic that detected when the address being output was in the IO range and clock stretched appropriately.

There are (as in still being made today I think) similar devices for the Apple II too - so it might be worthwhile looking for them.

I don't recall how mine handled video access but it was many years ago. I plugged it in and it all more or less "just worked". Mine was made by a company called Solidisk who also made sideways RAM expansion boards and other Beeb stuff.

So you ought to be able to make something up relatively easy using todays faster 6502s. Also changing the 6502 for a 65C02 would let you run Basic 4 too - which has much faster floating point.

-Gordon

I'm aware of those devices, but the end goal isn't a faster original Beeb, but a Beeb MOS compatible using RP2350(s) to replace most of the IO.

cheers,

Ray