6502.org

ttlworks, June 11. 2025

Me (ttlworks) and Frank (fhw72) had to stop with our chip dissections.

Remembering the MOnSter 6502 (which was built from FETs) which can run at 50kHz max.,
we spent some thoughts on what it would take to build something like a "6502 compatible"
CPU from bipolar transistors, aiming at 10MHz+.
//Note that there is a difference between "compatible" and 'compatible'.

The problem when using bipolar transistors is, that you can't build dynamic latches like when using FETs,
what considerably bloats the amount of components required.

A BSV52 based open collector Schottky clamped inverter with open collector output
(plus pullup resistor) could reach something like a 5ns propagation delay.

CTL (complementary transistor logic) is pretty fast, even when using BC847 and BC857,
it's sort of an outgrow of ECL emitter dotting.
CTL gate outputs require a pulldown resistor at the output,
but CTL is neat for building compact PLAs and compact AND/OR combination gates.
;
Note, that the bus lines in a real 6502 chip basically have pullup resistors and are tied to GND by FETs.
Means that when CTL is feeding a bus line, it injects current into the bus line from VCC and you have pulldown resistors.
So when building a 6502 like CPU with CTL driving the bus lines, this calls for low_active bus signals.

http://www.6502.org/users/dieter/mt15a/mt15a_3.htm
It's been nearly 20 years that I had built the MT15 transistor CPU,
actually it's been more than 6 years that I did PCB layouts at all.

Voltage drop in the supply lines when building a big CPU that drains a lot of current
from the power supply can become a serious topic, so it might be better to go with a +3.3V supply instead of 2.5V.
IIRC what limited the speed of MT15 to 500kHz was, that the inverters showed something like
a hysteresis in the input/output transfer curve that increased with frequency, and I never figured out exactly why,
but putting a resistor in parallel to the Schottky clamp diode helped (and I never figured out exactly why).
In theory, the two 1N4148 diodes in series in a MT15 inverter could be replaced with a red LED,
but I never tried, have fun with tinkering.

After considering how much effort building something like a 6502 CPU with bipolar resistors would take,
me and Frank decided against starting such a project, mainly because,
to quote Jetfire (the Transformer): "I'm too old for this crap."

So I only tried to make schematics and layouts for some modules,
and decided "to put that theoretical stuff somewhere" because somebody else might need it for his CPU hobby project.
You would have to tinker a bit with the resistor and capacitor values.
Have fun.

Layouts and schematics are done with DeadBird Eagle 6.4, because after 26 years of using Eagle,
to me placing/rotating components in KiCad 9.0 still feels a bit... impractical.

//But to me it looks like KiCad is heading for the right track, and with Eagle dead KiCad certainly is the future.
//Thing is, that if you are old enough spending any thoughts about the far future isn't productive.

Be warned, that a 6502 with full RDY logic might take 500+ transparent latches.

If you are using static RS flipflops based on transistorised TTL inverters,
that's going to be _big_.

and.sch, and.brd

+3.3V supply.

CTL AND gate, two inputs, expandable with external PNP transistors.
Output resistor on the module is optional.
Because you may want to build big AND/OR combination gates by creatively wiring CTL AND gate outputs together.

buf2.sch, buf2.brd

+3.3V supply.

Two CTL buffers, pulldown resistors at the outputs not included.
Thing is, that the outputs can be wired together for forming an OR gate.

driver.sch, driver.brd

+5V supply, when being creative 4 modules can be stacked, one inverting driver with high_active output enable.

Note that building (relatively) fast drivers which can handle capacitive loads requires "some black magic",
do don't expect this schematic to really work without some modifications...

nand.sch, nand.brd

+3.3V supply.

BSV52 based TTL NAND, open collector output with pullup resistor.
2 inputs, expandable with external PNP transistors.

stackpointer.sch, stackpointer.brd //one Bit.

+3.3V supply.

Two CTL outputs with enable.

Pulldown resistors at the CTL gate outputs are not included, because you might want to connect them to bus lines.

pla.sch, pla.brd

It's rather big. Note that a 6502 would require 10 such modules.

+3.3V supply, CTL AND based PLA with 22 (buffered) inputs and 15 outputs.

Pulldown resistors at the CTL gate outputs are not included,
because you may want to build big AND/OR combination gates by creatively wiring CTL AND gate outputs together.

That's all so far.
You are on your own.
Good luck.

Interesting, for sure. Thanks for sharing your work.

The FET-based dynamic storage is very dense, compared to traditional flop designs. Personally I'd wonder if you could keep the bipolar logic but use FETs for storage. After all, for speed analysis, there is just one storage node in a critical path (or, two halves: the back end of one and the front end of another.)

It must be a simple thing to estimate the number of transistors and calculate the current needed - I think it might be quite a large number!

Oh, and to note, Ferranti's ULAs (as seen in Sinclair and Acorn machines) are bipolar on the inside, and the core runs at a reduced voltage compared to the I/O. This can possibly make the bipolar circuits both faster and lower power, compared to running them from a full supply rail. (I highly recommend Chris Smith's book on the Spectrum ULA - a large amount of good technical detail and not all of it is specific to the Spectrum. http://www.zxdesign.info/book/)

Thanks, Ed.

The problem with logic level FETs is, that they have more capacitance than bipolar transistors,
what limits the speed.