Help understanding PLA decoder
Posted: Sun May 25, 2025 6:23 pm
Hello, I've made CPU simulations before and I've got a working 6502 sim using the function pointer jump table technique. That's no problem. I want to take my emulation and understanding to a lower level now, and implement a PLA-based decoder. I have made decoders for more regular architectures, like pipelined MIPS. But these address modes + the size constraints are stumping me.
From what I've seen online (I think it was 6502visualsim or something?) it has a 5-bit state machine plus 8-bit instruction opcode plus a clock line. I know I'm capable of making a big state machine, so my goal is to instead do something in the same ballpark - 5 or 6 bits. I've made some progress staring at patterns in the 6502 instruction set grid, where the low nibble is the column and the high nibble is the row.
I think I need to split the states into three groups: fetch the operands, then do the operation, then store the results. State chains from each group should be able to be mix-and-matched; every fetch-the-operands state chain ends up in the same final state, then from there it branches into all the do-the-operation states, which converge to a single state, which then branches into all the store-the-results states. But if I do that naively, there's waaaaay too many states, and the cycle timings are all too long. Like a simple AND #$nn would be 6 cycles (common start->load imm->common op start->send AND command->common result start->save to A), but it should only be 2.
Is there a trick or technique I'm missing? Any advice for how to organize it all? Any resources online picking apart the 6502's PLA design?
From what I've seen online (I think it was 6502visualsim or something?) it has a 5-bit state machine plus 8-bit instruction opcode plus a clock line. I know I'm capable of making a big state machine, so my goal is to instead do something in the same ballpark - 5 or 6 bits. I've made some progress staring at patterns in the 6502 instruction set grid, where the low nibble is the column and the high nibble is the row.
I think I need to split the states into three groups: fetch the operands, then do the operation, then store the results. State chains from each group should be able to be mix-and-matched; every fetch-the-operands state chain ends up in the same final state, then from there it branches into all the do-the-operation states, which converge to a single state, which then branches into all the store-the-results states. But if I do that naively, there's waaaaay too many states, and the cycle timings are all too long. Like a simple AND #$nn would be 6 cycles (common start->load imm->common op start->send AND command->common result start->save to A), but it should only be 2.
Is there a trick or technique I'm missing? Any advice for how to organize it all? Any resources online picking apart the 6502's PLA design?