6502.org

Posted: **Wed Mar 26, 2025 12:08 am**

Hi Guys,

I have just started on my next 6502 build and am building it a bit at a time on strip board.

I am at the point now where I have the CPU driven off a 2 Hz clock and monitoring the address lines after a reset, to make sure all is ticking over ok.

So far so good, but what I am noticing that sometimes happens if I manually short out the reset line to ground for around 10 clock cycles and release, it ticks over as expected and most of the time get to $FFFC / $FFFD and goes of to wherever (as expected with no ROM yet). But, occasionally doesn't hit the reset vector when shorting out reset to ground manually.

Which makes me wonder, does the reset ideally need to sync with a particular phase of the clock input? With the likely hood that my manual reset is crossing between clock cycles, can this upset the correct reset sequence?

The clock pulse is extremely clean and has rise/fall times of 2.4ns at the reset pin on the chip, with a 100 ohm resistor at the other side of the pin on the clock source with absolutely no ringing.

: example.png (1.31 KiB) Viewed 1875 times

Above is an example of a failed reset vector sequence.

Posted: **Wed Mar 26, 2025 12:35 am**

I think the problem was more so of when I was reading the address from the bus.

I was storing the value supposedly prior to the high/low clock transition.

Code: Select all

while(gpio_get(28) == 1)                // While high, store the address
{
     address = gpio_get_all() & 0xFFFF;
}
printf("Address: $%x\r\n", address);

But, I think that it was potentially querying the next address, if the Pico was too slow to keep up.

Swapped the test to get the address at the low/high transition now, which seems to be happy. But, I'll have to work out a better method so I don't poll incorrect data from the Data lines later on.

Still, would be interesting to know about the ideal reset phase, etc.

Posted: **Wed Mar 26, 2025 1:14 am**

The reset input does not care what the phase of the clock is or how the edges relate to each other timingwise. I have always disregarded phase and timing on it, and never had a problem.

Posted: **Wed Mar 26, 2025 1:29 am**

Awesome! That's great information to know.

I have always been haphazard with my resets too, only adhering to the length of the reset minimum requirements. Good to know that this is fine.

Many thanks!

6502.org

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