6502.org

In AppleII there is DMA access to RAM. It consists of stopping the 6502 clock. I have a question. For how long can you safely stop the 6502 clock in the LOW state in the MOS version?

I don't know for sure, but in the past I said
> note that it's the max cycle time which is the constraint here. The general advice is to go no slower than 100kHz for reliable operation. In practice you've probably got some tens of milliseconds before charge leakage starts to flip values, maybe more

The actual length of time before an important value decays will be a function of voltage, temperature, noise, manufacturing variation, and possibly also altitude and solar activity...

Highly anecdotal and "it worked for me", but when I was experimenting with overclocking my 6507s (so NMOS) I somewhat crudely unplugged a wire from one can oscillator into another.

The board stopped then started again - just carried on where it left off. I left it 10 seconds once to see what would happen - it just carried on.

No guarantee of anything though!

Did any peripheral for the Apple II actually use DMA though?

-Gordon

A related question is how long DRAM retains data without refresh - George Foot explored that here
Testing memory refresh failure

I'm curious as to why Apple didn't use the RDY pin for this, anyone know?

RDY has no effect during a write cycle with NMOS parts.

I want to connect a 65816 symulator (STM32H750) to the AppleII bus so that it works in DMA mode and does not disable the 6502.
This emulator has its own RAM but needs access to Video RAM and I/O.
Since the maximum amount of data to write to RAM that the symulator 65816 can write in one command is 2 bytes, I think that stopping for 2 cycles will not be a problem.


I will have to figure out how to prevent problems with MVN MVP

April 1st is still a few weeks away, but maybe you could find some time to rig up an external gate to trigger NMI when it sees those opcodes, then print "PLEASE DON'T DO THAT" in your NMI service routine (in APPLESCII, of course).

Apple's recommendation is 10 uSec but it really depends on the actual CPU in use. The recommendation is based on Rockwell CPUs with Synertek CPUs being good for 40 uSec. If you're talking about a IIgs, that uses a 65816 which is fully static so you can stop things for any length of time. I suspect that an actual MOS CPU would be similar to the Rockwell in timing.

Apple produced some tech notes covering detailed bus timing for DMA access. See https://mirrors.apple2.org.za/Apple%20I ... 989-09.pdf for details.

Many did. Any Z80 card using the original Microsoft softcard design or anything like it used DMA for access as there was no memory on the card. Many other replacement CPU cards did as well.

A few cards used for software piracy, er, preservation had their own CPU and used DMA.

Some other cards such as video input cards and debugging aids did as well.

Apple had their own DMA SCSI controller card too. I've been told that Apple's big demo for that card was a digitized version of the asteroid field scene from The Empire Strikes Back stored on a hard drive being pumped into an Apple IIgs' video and sound memory at full frame rate. Impressive if true. Some of the newer third-party storage controller cards made toward and after the end of Apple producing the II also use DMA.

I use AppleII Europlus and SY6502 processor, so Synertec.
I don't have 65816 but only its simulator running on STM32H750

https://stm32-base.org/boards/STM32H743 ... 7XX-M.html
I want to connect it as a card to my AppleII

Basically, I have to develop the interface, so there is a chance that I will finish it by April 1st

My simulator executes 65816 instructions in the shortest time of 250ns - longer about 500ns (does not emulate 65816 cycles exactly)
I want to get the fastest possible data transfer speed in DMA 1 byte per 1 6502 cycle, so if I send data to Apple2 RAM memory, then every few bytes I will have to perform one 6502 processor cycle to refresh its registers.

E.g. for 10us every 10 MVN or MVP instructions I will have to let the 6502 execute 1 cycle.