6502.org

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FillScreen:
TXA ;Color stored in X
;Start one more than needed because of DEX below
LDX #255 ;IE 255-1 is zero
FillScreenLoop:
INX ;This is unrolled so that there is a STA for each row of the screen.
;Display mapping has 28 bytes at end of each row unused.
;Display location = $2000
STA Display, x
STA Display +$80,x
STA Display +$100,x
STA Display +$180,x
STA Display +$200,x
..... <etc for all 64 lines > .....
STA Display +$1F80,x
CPX #98
BEQ FillScreenLoopEnd
JMP FillScreenLoop
FillScreenLoopEnd:
RTS

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FillScreen:
TXA ;Color stored in X
;We process half the lines in each loop so we can branch back within the range of a branch
;We decrement the counter so we don't need a comparison in each iteration
LDX #97
FillScreenLoop1:
;This is unrolled so that there is a STA for each row of the screen.
;Display mapping has 28 bytes at end of each row unused.
;Display location = $2000
;First loop processes just the odd lines
STA Display, x
STA Display +$100,x
STA Display +$200,x
..... <etc for all 32 odd lines > .....
STA Display +$1F00,x
DEX
BNE FillScreenLoop1
LDX #97
FillScreenLoop2:
;This time all the even lines
STA Display +$80,x
STA Display +$180,x
..... <etc for all 32 even lines > .....
STA Display +$1F80,x
DEX
BNE FillScreenLoop2
RTS

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.R1loop:;Read Bit
  lda #SD_MOSI                ; enable card (CS low), set MOSI (resting state), SCK low
  sta  VIA_PORTB 

  lda #SD_MOSI | SD_SCK       ; toggle the clock high
  sta  VIA_PORTB 

  lda VIA_PORTA                   ; read next bit
  ROL
  ROL RLECount
;7 more times for a byte

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  lda VIA_PORTA                   ; read next bit
  ROL
  ROL RLECount
;7 more times for a byte

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    ASL
    ora VIA_PORTA

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; SD card interface test
;
; using bitbanging for NormalLuser
;
; SD_CS = CB2
; SD_SCK = CA2
; SD_MISO = PA0
; SD_MOSI = PB7

SD_BIT_MISO = $1    ; on Port A
SD_BIT_MOSI = $80   ; on Port B

; The low nybble sets CA2 (SD_SCK) in pulse output mode
;
; The high nybble sets CB2 (SD_CS) to output high or low
; CS is active-low, so "on" means low and "off" means high
;
PCR_CS_OFF = $ea  ; CB2 low, CA2 pulse output mode
PCR_CS_ON = $ca   ; CB2 high, CA2 pulse output mode

...

sd_init:
    ; Set CA2 to output pulses on reads from Port A, CS unasserted
    lda #PCR_CS_OFF : sta VIA_PCR

    ; Disable latching and shift register
    stz VIA_ACR

    ; Set Port A to input on PA0, output on other pins; and output zero
    stz VIA_PORTA
    lda #$ff-SD_BIT_MISO : sta VIA_DDRA

    ; Set Port B to output on PB0, initially outputting high
    lda #SD_BIT_MOSI : sta VIA_PORTB : sta VIA_DDRB

    ; First we have to let the card initialise by sending it at
    ; least 80 clock pulses with CS and MOSI high
    ;
    ; We do this by sending 10 bytes of $ff - 80 bits - with
    ; CS unasserted

    lda #PCR_CS_OFF : sta VIA_PCR

    ldx #16 ; a few extras
initloop:
    jsr sd_readbyte
    dex
    bne initloop
...

sd_readbyte:
    ; Receive a byte into A, high bit first
    lda #SD_BIT_MOSI : sta VIA_PORTB ; set MOSI

    bit VIA_PORTA ; toggle the clock once at the start

    lda VIA_PORTA : asl
    ora VIA_PORTA : asl
    ora VIA_PORTA : asl
    ora VIA_PORTA : asl
    ora VIA_PORTA : asl
    ora VIA_PORTA : asl
    ora VIA_PORTA : asl
    ora VIA_PORTANH       ; read last bit without causing a clock pulse

    rts

sd_writebyte:
    ; Send A, high bit first
    sta VIA_PORTB : bit VIA_PORTA : asl
    sta VIA_PORTB : bit VIA_PORTA : asl
    sta VIA_PORTB : bit VIA_PORTA : asl
    sta VIA_PORTB : bit VIA_PORTA : asl
    sta VIA_PORTB : bit VIA_PORTA : asl
    sta VIA_PORTB : bit VIA_PORTA : asl
    sta VIA_PORTB : bit VIA_PORTA : asl
    sta VIA_PORTB : bit VIA_PORTA

    rts