How does a 6502 processor know when to stop F-D-E-U cycle?
Posted: Thu Nov 09, 2023 8:19 pm
I was wondering how does a 6502 processor knows when to stop the Fetch-Decode-Execute-Update cycle
Suppose I have a few lines of instruction say:
LDA $01
ADC $02
STA $0671
I get the program execution up to the first three instruction, but how does the processor knows after executing the third instruction here that it has to stop?
I searched a bit about it and found that in general, the program tells the O.S that is has executed successfully after which the O.S updates the Program counter to the next address of the next program. But I am not sure how this works in a 6502 processor.
Basically I am trying to make a 6502 emulator and wants to understand the termination logic for terminating the instruction fetch-decode-execute loop. Should I simply add a special instruction at the end of the program, and stop my loop when I encounter it? Or is there any separate instruction to halt the processor execution cycle.
Suppose I have a few lines of instruction say:
LDA $01
ADC $02
STA $0671
I get the program execution up to the first three instruction, but how does the processor knows after executing the third instruction here that it has to stop?
I searched a bit about it and found that in general, the program tells the O.S that is has executed successfully after which the O.S updates the Program counter to the next address of the next program. But I am not sure how this works in a 6502 processor.
Basically I am trying to make a 6502 emulator and wants to understand the termination logic for terminating the instruction fetch-decode-execute loop. Should I simply add a special instruction at the end of the program, and stop my loop when I encounter it? Or is there any separate instruction to halt the processor execution cycle.