Slightly OT: Is it just me?
Posted: Sun Aug 07, 2022 10:39 pm
Over the last couple of years I kind of got a little busy with life, but still had time to prototype and test a few interfaces for my 6502 designs. Got them all working as I wanted and finalized the schematics. Then recently I decided to have them made up into PCBs, so did the layouts and sent them off for manufacture. I was fairly confident they would be just as I wanted them.
Here is what I got back: From left to right: The first card is a PWM generator with parallel input and output plus a decoded bus access point. The next is video card based on the TMS9918, and the last one is an analog card with two ADC, two DAC and another decoded bus access point. I built them up, but even as I was building them and thinking about the CUPL code for the glue I either realized I missed some important signals, or left out a feature/alternate layout I seemingly can't live without.
For the PWM card I forgot to bring Phi2 into the GAL. I had also moved one of the output patterns without updating the Vcc and GND layers, effectively shorting them out. After fixing those (see bodges) and testing things out I realized something. The card provides two outputs. TTL level and a open drain via a 2N7000 MOSFET. Both worked as expected except I found did not like the inverted pulse width of the open drain output. In my mind a higher number should mean a wider pulse width. So now I have a new card coming that incorporates the corrections and changes.
For the video card I forgot to bring the Slot Select signal from the bus to the GAL. If it was the only card in the backplane that would not be an issue. To me though that defeats the whole idea of a backplane. That's the long bodge wire. The shorter one was as a result of me trying an experiment I eventually rejected. Also, while in use I really did not like the two pin video out and wished for an RCA jack. There is a corrected and updated board on the way.
For the Analog board I did not think things through 100% here either. My prototype had only 1 ADC and 1 DAC. The ADC was device 0 and I initiated the conversion by writing to it, then going back to read the result. The DAC was device 2 and was write only. For this board I wanted 2 of each and a buss access point. I also wanted ADC1 and DAC1 to be the same device # and ditto for ADC2 and DAC2. However, that left me with no way to initiate conversion on the ADCs. The bodge wire you see brings A0 to the GAL. This acts like a virtual 'register'. So if the ADC is at $8100, then conversion is initiated by a read to address $8101 with a subsequent read to $8100 to get the value. I also do not like the arrangement of the pins for the ADC inputs and wanted to update the silk screen and move the bus access connector back a bit. The DACs worked as expected. As before, a new board is on the way. Oh, the purple color was also an experiment. It looks okay.
So, this sort of thing is pretty much par for my course. I do occasionally get it right first go, but that is less than 25% of the time. Is it just me or do others have these experiences?
Here is what I got back: From left to right: The first card is a PWM generator with parallel input and output plus a decoded bus access point. The next is video card based on the TMS9918, and the last one is an analog card with two ADC, two DAC and another decoded bus access point. I built them up, but even as I was building them and thinking about the CUPL code for the glue I either realized I missed some important signals, or left out a feature/alternate layout I seemingly can't live without.
For the PWM card I forgot to bring Phi2 into the GAL. I had also moved one of the output patterns without updating the Vcc and GND layers, effectively shorting them out. After fixing those (see bodges) and testing things out I realized something. The card provides two outputs. TTL level and a open drain via a 2N7000 MOSFET. Both worked as expected except I found did not like the inverted pulse width of the open drain output. In my mind a higher number should mean a wider pulse width. So now I have a new card coming that incorporates the corrections and changes.
For the video card I forgot to bring the Slot Select signal from the bus to the GAL. If it was the only card in the backplane that would not be an issue. To me though that defeats the whole idea of a backplane. That's the long bodge wire. The shorter one was as a result of me trying an experiment I eventually rejected. Also, while in use I really did not like the two pin video out and wished for an RCA jack. There is a corrected and updated board on the way.
For the Analog board I did not think things through 100% here either. My prototype had only 1 ADC and 1 DAC. The ADC was device 0 and I initiated the conversion by writing to it, then going back to read the result. The DAC was device 2 and was write only. For this board I wanted 2 of each and a buss access point. I also wanted ADC1 and DAC1 to be the same device # and ditto for ADC2 and DAC2. However, that left me with no way to initiate conversion on the ADCs. The bodge wire you see brings A0 to the GAL. This acts like a virtual 'register'. So if the ADC is at $8100, then conversion is initiated by a read to address $8101 with a subsequent read to $8100 to get the value. I also do not like the arrangement of the pins for the ADC inputs and wanted to update the silk screen and move the bus access connector back a bit. The DACs worked as expected. As before, a new board is on the way. Oh, the purple color was also an experiment. It looks okay.
So, this sort of thing is pretty much par for my course. I do occasionally get it right first go, but that is less than 25% of the time. Is it just me or do others have these experiences?