6502.org

Posted: **Fri Jul 22, 2022 11:16 am**

Hi all;

I was reading through the instruction timing chart (table 6-5) of WDC's W65C02S datasheet (February 2004), as one does, and got a little confused when it comes to the behaviour of the BBRx and BBSx instructions.

It is my understanding that they have only 1 addressing mode which is really a kind of juxtaposition of zeropage and relative addressing (how it's described in Bruce Clark's 65C02 tutorial here. Some sources identify this as a bonefide addressing mode, but WDC just call it relative (e.g. c.f. table 6-4).

Looking at the documented bus behaviour of BBRx and BBSx, however, the confusing part is that these sets of of instructions have 2 slightly different entries, one classifed as relative and one classified as zeropage.

The first (relative) goes like this:

: WDC instruction timing chart entry for BBRx and BBSx, classified as Relative

Whereas the second (zeropage) goes like this:

: WDC instruction timing chart entry for BBRx and BBSx, classified as ZeroPage

I also note that the first (relative) description adds a note that an additional cycle is taken if the branch is taken, whereas Bruce's document mentioned in the above states that:

Quote:

Unlike other branch instructions, BBR and BBS always take the same number of cycles (five) whether the branch is taken or not

This seems to correspond better with the second (ZP) entry from the WDC datasheet.

So my question is whether there is some distinction in the instruction timing that I am overlooking that warrants these 2 different descriptions or whether it is simply an error in the datasheet.

Thanks in advance.

[Edit: This should have been posted in General Discussions but I cannot figure out how to remedy that so maybe a moderator can move it.]

Posted: **Fri Jul 22, 2022 1:15 pm**

Here's how the 6502 Decoder treats these instruction.

Code: Select all

   // Example: BBR0, $50, +6
   // 0 8f 1 1 1 <opcode>
   // 1 50 1 0 1 <op1> i.e. ZP address
   // 2 01 1 0 1 <mem rd>
   // 3 01 1 0 1 <mem rd>
   // 4 06 1 0 1 <op2> i.e. Branch relative target
   // 5 20 1 0 1 (<branch taken penalty>)
   // 6          (<page crossed penalty>)

The instruction is 5, 6 or 7 cycles, depending on whether the branch is taken, and whether it's to a different page.

This is certainly correct for the Rockwell implemenation, and I would expect it would be the same for the WDC implementation.

Posted: **Fri Jul 22, 2022 1:34 pm**

Yes, the instruction is 5, 6 or 7 cycles. With Bruce's approval, Garth & I have some edits on the go to correct that little error and to add more info re the C02's undocumented NOPs.

-- Jeff

Posted: **Fri Jul 22, 2022 1:43 pm**

I use the BBSx/BBRx instructions quite a bit. It's always been a bit confusing as various documentations do not match. The Eyes/Lichty handbook shows these instructions under the Rockwell section in the back of the book. They only show as 5 clock cycles to execute.

As these are relative branch instructions, one would expect an additional clock cycle to be added if the branch is taken, but I've not found any WDC documentation that describes this. Also, the extra clock cycle is the page boundary is crossed would also be expected.

6502.org

Instruction timing of BBRx and BBSx

Instruction timing of BBRx and BBSx

Re: Instruction timing of BBRx and BBSx

Re: Instruction timing of BBRx and BBSx

Re: Instruction timing of BBRx and BBSx