6502.org

So.. Things are going great for my new project of recording data to reels of tape, using something close to the Kansas City Standard. 1200/2400Hz, 4/8 pulses pr bit = 300 baud, with a leader byte of 7F.
Reception/loading I'm achieving by simply running the audio through a comparator and triggering a CA1 IRQ and using T1 to count the time between IRQs. It works! Yay! I'll throw together a video with the details "soon".

While I was at it I thought this was close enough to APRS / Bell 202 to use the same idea, however this uses 1200/2200Hz instead, meaning the 2200Hz pulses don't fit with the bitrate. For instance the unencoded byte $FE (LSB first) will consist of one long pulse and only 13 short pulses instead of the 14 it would've been for an even fit. Also APRS allows changing the frequency at offset phases - meaning the frequency doesn't just change at the zero crossing and sometimes messing up the counting because it edges on zero crossings.

Since data is NRZI encoded I shouldn't really run into 7 "1"'s in a row but it does happen when receiving flag bytes.

Right now I'm just trying to add the 14th pulse in software and see if that'll work well enough to receive a "perfect" APRS packet... I know it's far from optimal but getting it to work with just a single IC is part of the fun.

The 6522 datasheet recommends using T1 for timing async serial data but sampling a frequency is a different matter than sampling a level... I can't really wrap my head around checking the frequency without timing zero crossings. Maybe a 4046?

Any other suggestions for receiving Bell 202 either in software or hardware (assuming comparator + 6522 already available)?

I looked again for the diagram of the complete modem I made many years ago, and still could not find it, but pulled out an older version I did in about 1986, and made a small improvement on it (although I have not built this up).  So here's the idea for the demodulator (on the back of an envelope again):

The input comes from a circuit that amplifies and clips the incoming audio to make a 0-5V digital signal.  When it goes up, the outputs of those first two inverters go down, and the top one turns on the transistor, hard, immediately charging C2 up to +5V.  The transistor won't stay conducting more than a couple dozen microseconds though, because besides the fact that its base current is charging up C1, so is R1, and soon there won't be any base current, so C2 begins discharging again through R2.  How long it takes depends on R2's setting.  The setting should be around mid-range for 1.5kHz or 2kHz.  The exact setting will depend on the size of the hysteresis of the 74HC14 section there and how accurate C2's value is.  That rightmost 'HC14 Schmitt inverter's output will rise at the time-out period.  If the input frequency is above the threshold, the rightmost inverter's output will not have changed yet when the input goes low again and gives the FF a clock edge; but if the input frequency is below the threshold, the rightmost inverter's output will have changed by the time the next input falling edge comes.  The Q output of the 74HC74 goes to the UART's receive-data input.  If you need the opposite phase, use the Q\ (Q-not) output instead.

Very nice! Thank you!
Even better: I have a '74 left over from my PS/2 interface and also three '14 gates from buffering I don't need so it certainly won't affect board size much.

I'm worried I will run into the same issue for 1200/2200 though since it also relies on the zero crossings for changing Q?
When the frequency changes on the highest and lowest points of the sine wave, this seems to become unreliable.

I've tried to mark the issue. From falling edge to falling edge the period changes from 2200 Hz to ~1800Hz to maybe 1400hz and back to 2200hz because of the way the waves get chopped at zero crossings. Of course the waves themselves are only 2200 and 1200 Hz but sampling at zero crossing turns out to be a problem.
Again - not an issue for the tape interface that I've made to only transition on zero crossings, but APRS is more annoying than I thought...

I too suspect there'll be difficulty with the Zero-Crossing approach, at least in its simplest form. Garth's circuit is sufficient to appraise the delay from one rising edge to the next and determine whether that delay is above or below a certain threshold, and that's alright for a 1200/2400 scheme. But with a 1200/2200 scheme (ie, frequency changes not tidily aligned) I suspect "above or below a certain threshold" isn't enough information.

I think you would have enough information if you used a VIA timer to give a much more fine-grained appraisal of each Zero-Crossing delay. That is, describe each delay with an 8-bit value (say), rather than a 1-bit value.

Making sense of that stream of values will be tricky, though, because (as noted) the 1200/2200 Hz frequency changes are not tidily aligned. Maybe you should present the matter to our forum members as a Coding Challenge!

-- Jeff

I think timing the zero-crossings isn't such a bad start. But using the counting of the zero-crossings is causing a trouble. Perhaps better to accumulate the times-between-edges and match against the nominal baud rate.

I think it would be better still if a simple circuit could allow you to get an interrupt at both a rising and a falling edge.

Of course from a Bell perspective, trying to read a frequency-domain signal with a time-domain approach like this would raise eyebrows, at least. The "right" approach would be a pair of nicely tuned filters.

Well, I guess I'm not that far off using the CA1 irq and timing between edges. It's the software version of Garth's circuit.

Since we're only talking 1200 baud here, there's plenty of time to flip the CA1 trigger edge on every edge, meaning I get both edges - but I think I have to use all 16
T1 bits at 2 MHz as opposed to just using T1CH as I am now.

If I understand it correctly the PLL approach let's me sample the frequency independently of the zero crossings by using the 4046 as a frequency comparator.. Higher complexity, more precision... Worth it? Maybe...

It would be interesting to see if you could get anywhere with a PLL, but with only single cycle of the low frequency waveform I feel it might be a challenge.

I think once you have a stable timebase, from a timer and not from counting edges, it might be as simple as noting whether you've seen two edges in quick succession, or not. That's a binary question, with a single threshold, and should result in the right kind of bitstream. (You mention NRZI and flag bytes - not sure what kind of original signal you might be trying to recover.)

Sadly, it's not. When the baud rate and the frequency don't line up we will end up out of sync if we sample at the baud rate.
If I set T1 to trigger every 1/1200th of a second (starting after the first bit) for 2200Hz there will most times be two edges, but sadly sometimes only one.
Like my example of 01111111 will be one 1200Hz pulse but only 13 2200Hz pulses - meaning one of the bits only get a single pulse instead of two.

For the PLL I grabbed my copy of the CMOS cookbook and revisited the chapter on PLL's - Lancaster uses an example of measuring a 9Hz signal fast by introducing a divide-by-100 counter in the PLL.
I have no idea what I'll get if I set the VCO to 1700Hz and feed it the input from the comparator.. It certainly won't be happy with a sine wave.
Still... maybe?

Edit: The Bell202 signal in question is APRS https://en.wikipedia.org/wiki/Automatic ... ing_System

I wasn't thinking of counting edges within fixed time slots, but taking the times that edges happen, until a byte's worth of time has been accumulated, and then resampling the implied signal at the right times for the baud rate. In effect, a software UART. (It feels like I'd have to write heaps more to spell it out, and I'm ready for bed, so I won't do that now.)

You can still do it with a software UART.  There's some jitter in when the start bit starts, to start the clock, and some jitter in each bit's boundaries, but if you just sample in the (slightly erroneous) middle of each bit time, you'll stay out of the jitter area, and you'll be fine.  No errors.  By "jitter," I just mean a little uncertainty in the timing boundaries, not a lack of debouncing.  You don't need to count edges.

Seems to me we're all missing each other by a few bits here.. so please correct me. I think I get BigEd's idea - sample 8/1200ths worth of data and then putting everything in place retrospectively..

The problem I still have with Bell 202 here is that if your frequency -> UART implementation relies on counting edges, the error will in fact accumulate on the "edge counting side" - not on the UART side.

I've pasted a 1200Hz square wave under the attached data here to illustrate the issue - one of these bits only have a single zero-crossing, and it's not easy to see which one. (The data in question is the sample from Wiki)

I haven't made a modulator for APRS but I don't think I can do it with T1+PB7 like I have with KCS 300+1200baud because the frequency will inevitably change before the bit period is over and a 6522 T1 can't do that - I will absolutely try to breadboard Garth's modem sketch if I decide to make one.

I apologize for muddying the water

The reel 2 reel seems very forgiving. I haven't tried 1200 baud yet but no issues at 300 and 3.75IPS - I have yet to see any issues with T1 output and a 4 stage RC filter. The only issue here is the amplitude variation when the time comes for demodulation - but a zero crossing doesn't care about amplitude so as long as the offset isn't too bad it seems to work wonders.

APRS is the HAM packet radio system and uses the Bell202 standard because it was easy to get the surplus 1200b modems in the 80's.
It's still very much in use today - even the ISS will spit out packets if you point your Yagi in the right direction.

Since the frequencies are similar I took a detour down the rabbit hole of demodulating APRS/Bell202.

I'm quite intrigued by this challenge, and I think I do have an answer, which is of course entirely theoretical... but let me try to say a bit more.
I think the reason demodulating from your diagram looks challenging is that the 1200bps boundaries you've drawn are imposed from outside - they don't come from the data, or more specifically, from its zero-crossings.

Let's see if I can do a worked example, and see if that works out in any useful way.

You've drawn a regularly-sampled analogue signal incoming. I'm going to use the ticks from that as if they were timer counts, and just look for zero crossings. I'm counting by hand so there might be some mistakes, but I expect this idea not to be too sensitive to that - it's the same as a slightly fast tape, if I undercount.

First zero crossing at sample 2.
Next at 12. Then at 22. Then 35.
Then at 53. Then 69. Then 79, and then I lost count...
... but it's clear that the high frequency crosses zero every 10 samples.

So, with that data collected from timer readings, driven from polling loops or edge-sensitive interrupts, we want to construct some idea of the frequencies. Or, rather, the wavelengths.

It takes two zero crossings to make one wavelength, but note that we don't know how the signal might transition between low tone and high tone. It might even have discontinuity. But all we need are two things: an estimated time of a bit-cell transition, and then the presence or absence of a high tone. We don't actually care too much about the low tone for this purpose.

Here's the series again: 2, 12, 22, 35, 53, 69, 79, 89, ...
So the half-periods are the differences: 10, 10, 13, 18, 16, 10, 10, 10, 10, ...
So the full periods are (in a sense) one of two possibilities:
- starting at time 2, wavelengths of 20, 31, 34, 26, 20, 20, 20, ...
or
- starting at time 12, wavelengths of 23, 34, 20, 20, 20, 20, ...
and what we want is the timestamp which estimates when the high tone stopped (and became a low tone)

If the nominal period of high tone is 20, we could choose 24 as a threshold for the longest period we're prepared to call high.

So the 23 period which starts at time 12 and ends at time 35 counts as high.
And the 31 period which starts at time 22 does not count - we'll call it low.

So, we say that we've found a low-to-high transition at time 35.

Now we can sample our capture at subsequent mid-points of bit cells, indexed from time 35, or time 35 less one bit-time, which is 40 units on this scale.

So the sampling should be done at time 15, 55, 95, and so on.

Now we look again at our zero-crossing records and estimated wavelengths, at those times, and ask the question "is this within a high tone"

Time 15... yep, that's within a reconstructed 20-long wave
Time 55... nope, that's within a 34-long wave
Time 95... yep, that within a 20-long wave

So, that's my sketch of how we get from timestamps of zero-crossings, to estimated bit cell boundaries, and reconstructed wavelengths, which we can sample at bit cell midpoints.

It might well be that a simpler approach which only sees rising edges (or falling edges) would work just as well, but that's working with less information, and we've already lost a lot by turning our signal into a square wave.

As you note, it might be that you can use a single input and keep switching between rising and falling edge triggering.

It might be that analogue circuitry to detect either edge and emit a short pulse on the zero crossing wouldn't be too hard to mark.

Note that DC bias in the signal, or asymmetry in rising and falling rates, might push the timings of zero crossings in one direction or another.

When pre-processing difficult tape captures, I've found it useful to apply a high-pass filter to remove DC bias, and hum, and also to boost the two expected data-carrying frequencies.