6502.org

My copy of the Scanlon book, 6502 Software Design, is in. I was just thrown for a loop by the last sentence in this paragraph on page 18, so I'm posting my thoughts here in case it trips anyone else up (bold emphasis mine):
Huh? It seems to claim that for (multi-byte) instructions that contain an address, the address goes into the program counter? If that's the case, then LDA $0000 would set the PC to $0000 instead of loading the value at $0000 into A. Or is $0000 considered "data" and goes into the ALU in this case? I think only the various jump and branch instructions are the kinds of address-carrying instructions the author was thinking of that sometimes change the PC. But many instructions, like shifts, rotates, loads, and stores, etc., do not otherwise change the PC apart of allowing it to increment to the next instruction. Is my understanding correct?

Yes.

-- Jeff

I think I remember, when first getting to know the 6502 (the first micro I did get to know) having a little bit of confusion between the Program Counter and the Address Bus. At the point of fetching the first byte of each instruction, the PC value is driven to the address bus, and that's fine. But in the subsequent cycles, as you note, the address bus may be used for read or write accesses according to what the instruction is, and it does not reflect the PC value.

I think what's happening is a bit of confusion between a very software way of looking at code, and a more hardware way of understanding what the system is doing. In particular, thinking instruction-by-instruction is one thing, and thinking cycle-by-cycle is another.

In my experience, that confusion goes away eventually. It's best not to write a book while confused!

(It is true for JMP and JSR that the two bytes of operand will find their way to the PC. So the sentence might also be fixable if it talked about a program address, rather than an address.)

I think Ed's comment about the software vs. hardware view of the process is on target. The sentence in question causes some confusion by not identifying that the second and third bytes must be held in internal registers / latches that are not visible to the programmer. It is from these internal registers / latches that the data is routed as described in the referenced text. Given the two phase nature of the 6502 machine cycle, it is possible to reduce the number of temporary registers to reduce the transistor count. Since latches are the primary memory devices used within the 6502, it is possible to transfer one operand, from a single internal temporary operand latch, to the low address latch, and simultaneously transfer the second byte of the address from a data input buffer, implemented as a latch, to the high address latch. Simultaneously, this 16-bit address can be loaded into the program counter. Refer to the 6502 block diagram provided at this link.

This flow through feature of latches can be used very effectively to reduce the number of memory elements required. However, it requires precise control of the latch control signals, which can be difficult to achieve when high rates, or short delays, are required. Thus, modern design practices avoid the use of latches and instead rely on registers, which do not allow the flow through action described above.

In the case of my 6502/65C02 FPGA-based emulation, I use two registers which I name OP1 and OP2, which hold the first and second operand bytes of an instruction, respectively. When I load OP1, my implementation either zeros OP2, or loads it with all 1s based on the most significant bit of the operand byte being loaded into OP1, i.e., sign extension. OP2 is the sign-extension of the OP1 for all branch instructions, and simplifies the implementation of the PC-relative addressing associated with the 6502/65C02 branch instructions.

When I "execute" the instruction after all required operands are present in the operand registers, my implementation effectively performs the actions described in the referenced text: OP2, OP1 are either used to modify the PC, generate a direct / indirect operand address with or without indexing, or supply an immediate data to the ALU which may simply pass it through to the A, X, Y, or P registers.