6502.org

Just curious -- are there any MOS 65xx processor wafers still in existence somewhere, like a museum?

I am interested in how many die per wafer and what the process control monitors (test structures in place of a die) contained.

If you search for "6502 four inch wafer" you will get some images and descriptions - usually Rockwell wafers by the look of it, and possibly not the original NMOS 6502 but a later 65C02. If these were on a finer process, the die will probably be smaller than the originals, and the die per wafer correspondingly higher.

You will also find a few forum posts - there are places where collectors congregate, and it might be worth asking there.

I also searched for three inch wafers - I did at one point think that the original MOS production was on three inch, but I can't presently confirm one way or the other.

We do know that MOS' original plan was very aggressive on die size, and most likely that's because the number of die per wafer is a discrete function of die size, and if the die are relatively large compared to the wafer, it's got big steps in it. So a small increase in size causes a big decrease in die per wafer, which is a big increase in cost.

Sorry I don't have anything concrete for you.

The Computer History Museum has taken oral histories, at different times, of both Chuck Peddle and Bill Mensch.

Peddle says he doesn't remember the wafer size. In the Mensch history we get the following:

I found some previous threads which relate to die size, wafer size, process node, and yield:

A (Long) Conversation Chuck Peddle, Bil Herd, Jeri Ellsworth
Process geometry information of original 1975 MOS 6502
interrupt latency (and 6502 die size)

There are details I've since forgotten...

(In some of them there has been some link rot, but in some cases later posts pick up the slack.)

Edit: see also
Interesting findings in the team6502 trove
which mentions 3 inch wafers

Thanks, I've seen the Rockwell wafers on ebay + chipscapes (Steve Emery sent me some nice photomicrographs) but was wondering what the difference was on MOS Technology wafers. WorthPoint (archived eBay listings) had a 6510 wafer listing: https://www.worthpoint.com/worthopedia/ ... 1811575429 but who knows who owned it once and who owns it now.

I've already been in contact with Bill Mensch directly, he's given me some good information about what kinds of stuff was on the PCMs but I'd like to find a picture. (He has several early 6502 chips, no wafers.)

I was hoping some museum might have one.

Just for interest, using the die size you gave in this thread and the three inch wafer size mentioned in this one, plugging them into this die-per-wafer estimator site, we get 138 die per wafer. This is consistent with the idea of getting 100 good die per wafer, which would be a 73% yield.

Edit: if and when MOS moved to using four inch wafers, the estimate goes up to 270 die per wafer - nearly double. With the reduced die size of the Revision D as well, the estimate goes up to 444.

I happen to have a MOS6569 and a MOS6523 wafer, but not a 6502. I did get an offer for a MOS6502 a few years back, but it was too expensive for me at the time.

I searched my email and I can see that he offered med a 6502D, a 6510R6 and a 6581R4 wafer. The 6502D had 28 chips in one direction and 25 in the other. There are flats on a Silicon wafer that makes it somewhat shorter in one direction. All chips close to the wafer edge (or at it) were marked as bad.

All these wafers are 4 inch.

Handy numbers - thanks!