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Hi all;

I am measuring a solid 5V logic H level from the address bus output of a R65C02 that I am doing a project with, but the chip is designed to work at TTL levels and the Rockwell datasheet promises only at least 2.4V for a logic H.

In general I am interfacing to it using HCT logic, but as I have a couple of unused HC gates in packages already in use on the board, I was thinking to use them, interfacing them to the MPU with pullup resistors as per the standard TTL-to-CMOS play book. Everything is 5V.

However, I am a little uncertain how to determine a suitable value for those pullups. I expect relevant factors are the impact on sharpness of the transitions (I'm just running at 1MHz presently) but also the impedance or current sink capability of the MPU's outputs, neither of which I can find specified in the datasheet.

I've seen 1k mentioned several places describing TTL-to-CMOS in general terms, but it seems a little hard given that I basically observe 5V H levels anyway, and I don't want to have the MPU sink more than it has to either.

Any rules of thumb or pointers to information about how to actually calculate a suitable pullup value from you experienced people?

Thanks in advance for your input.

1kΩ is a typical value for a pull-up resistor for use with 74xxx and 74LSxxx plus many other 74 series ICs. 74xxx and 74LSxxx series TTL logic and NMOS chips are typically far better at sinking current than sourcing current on an output pin.

With 74HCxxx and 74HCTxxx series logic, being CMOS, it has significantly higher input impedance on it’s input pins. Hence the main thing that a pull-up resistor has to overcome is the stray capacitance of the board wiring.

For slow systems where the rise time of a signal is not critical, a value as high as 100kΩ can be used. However, a slowly rising signal is not good where there are other faster signals. So a more practical value is 3.3kΩ.

However, although this should be fine in a 1MHz system, it may not be at significantly faster system speeds if the length of the wiring is anything other than very short. And even then it may be marginal.

I suspect that a R65C02 would not have a problem with a 1kΩ pull-up resistor, as often the output drivers are more powerful than the datasheet implies. Remember datasheets often only give the minimum specification that it is designed to work at.

Mark

For more on the effects of a pull-up resistor connected to stray capacitance, read through the
RC Integrator, RC Waveforms and RC Charging Circuit sections in this tutorial.

Mark

Firstly let's be clear that a chip's input characteristics and its output characteristics are two separate subjects.

Chips from families such as 74 and 74LS fall within the TTL spec for both their inputs and outputs. Their inputs are allowed to require a certain current in order to pull low, they require virtually no current to go high, and the transition point for inputs is around 1.5 volts. Their outputs, as you'd expect, are adequate for driving such inputs. But they don't over-deliver. That is, the outputs are quite strong (low impedance) when pulling low, but their ability to pull high is rather limited, both current-wise and voltage-wise. And that's OK, because 74 and 74LS series inputs don't require much voltage or current to perceive a high.

Chips from the 74HCT logic family also fall within the TTL spec for both inputs and outputs. The input transition point is around 1.5 volts, and that's what enables an HCT chip to reliably "hear" the wimpy logic High that an actual LS chip will output. (You may wish to refer to my thread, TTL Compatible... NOT! ( modern WDC CPU's ). I'm attaching one of the illustrations below.)

Output-wise, chips from the 74HCT logic family not only meet the TTL spec; they actually exceed it, and are documented as doing so. That is, you can expect an HCT output in the High state to go pretty well all the way to Vcc, and even source a fair amount of current while doing so. Clearly this is an output that requires no pullup resistor.

You've asked for advice about your R65C02, and I suggest you deal with it just as you would a 74HCT series device, both input-wise and output-wise. To achieve (near) rail-to-rail swings, the R65C02 outputs require no pullups or logic-level converter ICs, even though the datasheet fails to offer you assurances in this regard (ie, the output logic High level). The R65C02 was made at a time when one could safely assume that any CMOS device would have outputs that offer (near) rail-to-rail swings.

Be warned that many modern CMOS devices powered by 5V don't feature rail-to-rail output swings. Regarding modern 5V CMOS I don't recommend that anyone assume that the outputs will over-deliver. Certainly I and other forum members commonly see modern 5V CMOS RAMs and PLDs whose output-High is 3-volts-ish even with no load applied. The datasheet warns you not to expect rail-to-rail swings, and that's the straight poop -- many modern 5 Volt CMOS chips won't give rail to rail output swings. It's as if the chip internally runs on approximately 3 volts, and I suspect that is actually the case. Certainly something about the internals is different compared to old school CMOS. To be clear, it's specifically the 5 Volt modern CMOS you need to watch out for. In regard to modern CMOS chips intended to operate on 3.3V or less, I'm not aware of any that don't deliver rail to rail outputs swings.

Despite what the R65C02 datasheet says (actually fails to say), I'm sure you can expect rail-to-rail output swings (and you yourself have measured a solid 5V logic H). They just didn't bother to document it (probably because it was a 74LS world back then, and 74LS doesn't require rail-to-rail voltage swings).

-- Jeff

Thank you all for your feedback. I'm taking several points from this:

1. When an IC is declared "TTL compatible" it's more of a "for some values of TTL" statement than a formal declaration of adherence to the exact TTL thresholds.
2. You need some kind of historical awareness of what characteristics to reasonably expect fron an IC, fx in terms of output voltage swing, not just, say, whether it's built using CMOS.
3. For my particular design there should be no issue driving some HC logic from the MPU outputs without pullups, provided the design is not marginal in other respects.
4. For cases where pull-ups are needed, the main factor to consider is the impact to the edges which when interfacing to high impedance inputs can be modelled as the RC effect of the pull-up and the combined capacitance of what is connected to the output (traces and gates).

Thanks again and happy holidays.

Looks like you've gotten the right message on all four points.

Points 1 and 2 relate to what can be expected from datasheets. It's important to understand the circumstances and motivations of the people who write them. And their inclination is to be cautious, partly because there are various flavors of TTL, such as standard 74 series, 74S series, 74LS, 74ALS, 74F and so on. Because it's intended that these be able to interoperate, they all use pretty much the same voltage levels. But the amount of current required at an input or available at an output varies widely, so there's no such thing as formal declaration of adherence in this regard.

Another inclination is to conserve effort (be lazy)! If most of their customers only require a TTL Voh, and have no concern about rail-to-rail swings, then the ability to swing rail-to-rail, though perhaps very real, won't get documented in the datasheet.

-- Jeff