6502.org

Posted: **Sat Oct 30, 2021 2:09 am**

What is a phantom bit? I see that the e bit on the 65816 is referred to as a "phantom" bit. Does it not actually exist as flip flop in hardware anywhere?

Posted: **Sat Oct 30, 2021 2:15 am**

It exists, but since the processor-status register P is only 8 bits wide and there are 9 status bits on the '816 and the emulation bit is seldom accessed or needed to be pushed and pulled, you have to set or clear the carry bit and then exchange it with the emulation bit with XCE.

Posted: **Sat Oct 30, 2021 3:15 am**

Ok thanks, so it's like musical chairs trying to cram more bits in there.

Posted: **Sat Oct 30, 2021 4:45 am**

jeffythedragonslayer wrote:

Ok thanks, so it's like musical chairs trying to cram more bits in there.

Correct.

The reason SR (aka P, which it is hardly ever called in machine language monitors) is 8-bits wide has to do with the 65C02 emulation mode and Apple's influence (meddling, some might say) in the 65C816's design process. Already having a 16-bit ALU, it would have been trivial to give the 816 a 16-bit SR and thus expose the e bit as a separate entity. However, that would have meant SR would always be a 16-bit register, even in emulation mode. Ergo emulation mode would not have been (almost-true) CO2 emulation, as the sequence of PHP - PLA, for instance, would have not worked as it would in a real 65C02.

As Garth noted, software seldom does anything with e. Most native-mode software immediately switches the 816 to native mode with the CLC - XCE sequence, and that is the only time e is touched. As the 816 comes out of reset in emulation mode, the programmer doesn't have to do anything if he wants to stay in emulation mode.

Posted: **Sat Oct 30, 2021 5:29 am**

Cool. I suppose the B flag is another one of these phantom bits?

Posted: **Sat Oct 30, 2021 5:34 am**

Not in the same way. The b flag is only a position in the status byte pushed onto the stack when there's an interrupt, so you can tell, by reading the stacked status byte, if the interrupt was caused by a BReaK instruction. (See my 6502 interrupts primer.) The e flag does exist on the processor though.

Posted: **Sat Oct 30, 2021 6:26 pm**

GARTHWILSON wrote:

Not in the same way. The b flag is only a position in the status byte pushed onto the stack when there's an interrupt, so you can tell, by reading the stacked status byte, if the interrupt was caused by a BReaK instruction. (See my 6502 interrupts primer.) The e flag does exist on the processor though.

Furthermore, the 65C816 running in native mode has no b flag bit. The m and x bits that determine register widths take up the places that would be "held" by the b and the unused bit in the 65C02's SR. In emulation mode, the 65C816's SR looks and functions like SR in the 65C02.

Since the 65C816 has no b bit in native mode, it differentiates between an IRQ and a BRK instruction by giving the two separate vectors. Hence the stack sniffing required in a 65C02 interrupt handler to figure out if the interrupt was hardware or software is unnecessary.

Posted: **Sat Oct 30, 2021 8:22 pm**

...further improving the efficiency of the '816.

Posted: **Sat Oct 30, 2021 11:23 pm**

GARTHWILSON wrote:

...further improving the efficiency of the '816.

It's interesting to note that although the 65C816 in native mode has a more complex response to interrupts than the 65C02, the elimination of the need to differentiate between an IRQ and a BRK with a stack sniff means the 816's IRQ handler can be smaller and faster.

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