Error in 6502 IDE (Kowalski)
Posted: Sat Jul 03, 2021 9:40 am
When I compile the source got a strange message,
ERROR E022: Phase error-inconsistent label value between phases "SINOVF" ....
The code is straight from a rom listing.
Is this an error of the compiler?
This is my code.
Thanks for any help.
ERROR E022: Phase error-inconsistent label value between phases "SINOVF" ....
The code is straight from a rom listing.
Is this an error of the compiler?
This is my code.
Thanks for any help.
Code: Select all
ROMBASE =$D800 ;STARTING ADDRESS OF F.P. ROM
FPREC =6
NSCF =6
;
; BASE PAGE DEFINITIONS
;
SGNFLG =FCHRFLG
XFMFLG =DIGRT
FR0 =$D4
FR0M =$D5
FRE =$DA
FR1 =$E0
FR2 =$E6
FRX =$EC
EEXP =$ED
NSIGN =$EE
ESIGN =$EF
FCHRFLG =$F0
DIGRT =$F1
CIX =$F2
INBUFF =$F3
Z1 =$F5
Z2 =$F7
Z3 =$F9
RADFLG =$FB ;0=RADIANS, 6=DEGREES
FLPTR =$FC
FPTR2 =$FE
FDIV = $FFFF
FSUB = $FFFF
FMUL = $FFFF
PLYEVL = $FFFF
;FLOATING PT ROUTINES' NON-ZERO PAGE RAM (NEEDED ONLY IF F.P. ROUTINES CALLED)
*=$57E
LBPR1 *=*+1 ;LBUFF PREFIX 1
LBPR2 *=*+1 ;LBUFF PREFIX 2
LBUFF *=*+128 ;LINE BUFFER
PLYARG = LBUFF+$60 ;POLYNOMIAL ARGUMENTS
FPSCR = PLYARG+FPREC
FPSCR1 = FPSCR+FPREC
FSCR = FPSCR
FSCR1 = FPSCR1
*=$1000
SINERR SEC
RTS
SIN LDA #04
BIT FR0
BPL BOTH
LDX #2
BNE BOTH
COS LDA #1
BOTH STA SGNFLG
LDA FR0
AND #$7F
STA FR0
LDA #>PIOV2
CLC
ADC RADFLG
TAX
LDY #<PIOV2
JSR FLD1R
JSR FDIV
BCC SINF7
SINOVF RTS
SINF7 LDA FR0
AND #$7F
SEC
SBC #$40
BMI SINF3
SINF6 CMP #FPREC-2
BPL SINERR
TAX
LDA FR0+1,X
STA XFMFLG
AND #$10
BEQ SINF5
LDA #2
SINF5 CLC
ADC XFMFLG
AND #3
ADC SGNFLG
STA SGNFLG
STX XFMFLG
JSR FMOVE
LDX XFMFLG
LDA #0
SINF1 STA FR1+2,X
INX
CPX #FPREC-3
BCC SINF1
JSR FSUB
SINF3 LSR SGNFLG
BCC SINF4
JSR FMOVE
LDX #>FPONE
LDY #<FPONE
JSR FLD0R
JSR FSUB
SINF4 LDX #>FPSCR
LDY #<FPSCR
JSR FST0R
JSR FMOVE
JSR FMUL
BCS SINERR
LDA #NSCF
LDX #>SCOEF
LDA #<SCOEF
JSR PLYEVL
LDX #>FPSCR
LDY #<FPSCR
JSR FLD1R
JSR FMUL
LSR SGNFLG
BCC SINDON
CLC
LDA FR0
BEQ SINDON
EOR #$80
STA FR0
SINDON RTS
FLD1R STX FLPTR
STY FLPTR+1
FLD1P LDY #FPREC-1
FLD1L LDA (FLPTR),Y
STA FR1,Y
DEY
BPL FLD1L
RTS
FLD0R STX FLPTR
STY FLPTR+1
FLD0P LDY #FPREC-1
FLD01 LDA (FLPTR),Y ;!
STA FR0,Y
DEY
BPL FLD01
RTS
FMOVE LDX #FPREC-1
FMOVE1 LDA FR0,X
STA FR1,X
DEX
BPL FMOVE1
RTS
FST0R STX FLPTR
STY FLPTR+1
FST0P LDY #FPREC-1
FST0L LDA FR0,Y
STA (FLPTR),Y ;!
DEY
BPL FST0L
RTS
PIOV2 .BYTE $40,$01,$57,$07,$96,$32 ; PI/2
FPONE .BYTE $40,$01,$00,$00,$00,$00 ; 1.0
SCOEF .BYTE $BD,$03,$55,$14,$99,$39 ; -0.00000355149939
.BYTE $3E,$01,$60,$44,$27,$52 ; 0.000160442752
.BYTE $BE,$46,$81,$75,$43,$55 ; -0.004681754355
.BYTE $3F,$07,$96,$92,$62,$39 ; 0.0796926239
.BYTE $BF,$64,$59,$64,$08,$67 ; -0.6459640867 