6502.org

Can somebody tell me what is wrong with this? VIA_IRQ is from a WD65C22 (S variant), ACIA_IRQ is from an MC68B50P and IRQ is connected to the WD65C02's interrupt pin. If I jumper either of the irqs to the output of the inverter then that interrupt goes thru to the processor. As wired, the IRQ line is permanently high. I have replaced both the hc00 and hc04 and metered the traces for continuity all's good but still no worky... I'm at a loss of what else could be wrong with this. Any ideas?

If you need a pullup on the VIA IRQ, you might well also need one on the ACIA IRQ. If the point is that these are open-collector, then they need a pullup.

But by the same token, if they are open-collector, they can both be directly connected to the IRQ input, and share a single pullup. The point of open-collector is that the device's output pin is only able to drive low, or not drive at all. Tying two together, with a pullup, makes an AND gate.

Thank you BigEd, from memory I remembered it as being "TTL compatible". Going back to the data-sheet after your reply I saw that it was "TTL compatible, open-drain (no internal pullup)". So I added a 3.3k resistor on the back of the pcb to pin 10 and 5v and now it's working fine.

Please forgive my potential ignorance, but if an output is low if either input is low, isn't that pretty much the definition of AND?

Mike, what you say is necessary, but not sufficient for an AND. If either is low, the result is 0. However, if both are low the result is also 0. The defining characteristic of an AND is that it is 1 only if both inputs are 1.

Logical AND: Logical OR: If we are dealing with negative logic, wired OR is pulled up normally, and drops low if any (or both) of the inputs go low:

Negative logic OR: Which looks a lot like positive logic AND, doesn't it? As they used to say in the Soviet Union at the end of televised children's competitions always ending in a tie, 'friendship wins'.

Thanks for the advice BDD, but I had a spare 74hc00 gate available and there's no room on the pcb for another 14pin dip. I'm not that concerned about the 2-gate delay, the board is running at only 2Mhz and after look at some of the interrupt priority circuits out there a 2-gate delay looks to be nothing in comparison to some.

How about using two diodes and a resistor to form a diode gate, instead of 74xx gates? Timing parameters are not important in this case - CPU cycle is an order of magnitude longer than any gate delays.

I'm crap at analog electronics stuff so I didn't even think about that