6502.org

Hey everyone!

I'm currently designing/testing my own 65C02 computer (inspired by Ben Eater) and thought I might post it here.
I wanted something versatile and fun to play with while learning assembly language and the 6502 seemed a good choice becuase of its already big community.

I put a lot of chips in it because I had some of them lying around. Also I always add a bit too much to my projects, just in case

Here are some specs of my computer:

Clock:
- Single Step
- NE555 timer (~5Hz .. 50kHz)
- Oscillator (currently 1MHz)

Memory Map:
0000 - 3FFF = Banked RAM
4000 - 7EFF = Common RAM
7F00 - 7F0F = PIA
7F10 - 7F1F = VIA1
7F20 - 7F2F = VIA2
7F30 - 7F3F = VIA3
7F40 - 7F4F = ACIA1
7F50 - 7F5F = ACIA2
7F60 - 7F6F = VGA GPU (will be an FPGA)
7F70 - 7F8F = SID
7F90 - 7F9F = IO9
7FA0 - 7FAF = IOA
7FB0 - 7FBF = IOB
7FC0 - 7FDF = IOC
7FE0 - 7FFF = IOD
8000 - FFFF = ROM

Banked RAM is 32 pages, I decided to bank the ZP and Stack as well, so every "task" later can have its own. Maybe a dumb idea, maybe good, I have to see how this will turn out....
I also added a BluePill-Board with STM32 microcontroller as embedded USB logic analyzer, so I can trace the program while the clock is slower.

PIA is for 2 Ports LEDs out (also on pin headers for general IO)
VIA1 is controlling the RAM banks as well as interfacing with the LCD (up to 4x40 char LCD)
VIA2 is 8 buttons as inputs (diode-ORed to CB1) as well as 8 interrupt lines (diode ORed to CA1), connected to IRQB on the 6502
VIA3 is currently only connected to pin headers (also connected to NMI on 6502), might add a PS2 keyboard to this one
ACIAs have Pin headers for the 5V serial signals as well as 2 MAX232 each for RS232 (each one connected to an interrupt)
GPU - IOD are expansion ports on the main pcb.
VGA GPU i will be another project. I plan to realize a VGA GPU on an FPGA for 640x480 display. This is postponed due to me still have to learn VHDL better....
SID is reserved for a 8580 SID I have lying here, will be the sound card.
the rest of IO-spaces can be used for whatever (one idea is hooking it up to an ESP32 for internet connection)
ROM is.... well.... ROM... EEPROM 28C256

I also added LEDs to the address and data bus, as well as RWB and Clock

I started this project out of fascination and boredom, also because I was inspired by Ben Eaters Breadboard computer (actually I tested the schematic on breadboards too), but since I'm currently studying to become a state certified technician (in electronics), I will use this project as my finals work.

If you have any questions, feel free to ask.
Currently I'm programming the libraries for the ICs and LCDs, writing or porting a small OS to it would be awesome, but as I'm still learning assembly, it can take some time...

and here is a picture of my computer ^^

Welcome! That's really impressive - what kinds of things have you managed to run on it so far?

Banking the bottom 16k is an unusual choice, so it will be interesting to hear how you get on with making use of that. I'm sure it can be made to work.

So far I'm just writing libraries and test-codes. PIA library and VIA library (mostly just initializations, timers will come soon) are working as well as a library for the 2x16 character lcd in 4bit mode. I have a connector for a 4x40 char LCD as well, but this is essentially 2 seperate displays in one, so I have to see how I'll manage to do that. but both displays are responding and displaying text, so I can build on that.

Next will be the interrupt routines, then I'll implement timers, after that I think are only the ACIAs left.

when I confirmed everythin working, I'll try to write some small OS with a simple round-robin task queue and will make use of the cc65 assembler, currently only using the ca65....

since I try to do everything from scratch there is quite a learning curve to it, so progress will be slow, but it's honest work

Wow very impressive indeed! What are you planning to do with it? I’m also wondering: why you have 3 VIAs and two serial chips ? You can control a whole lot of stuff with that. 6502 robotics maybe ?

@jfoucher
as I said, I had these chips lying around and finally wanted to do something with them. I did a lot of dumpster diving once and found these in nearly pristine condition...
I know I already have more IOs than I ever need, but I like to think a bit easier here... PIA ist just output for me (since the PIA registers are somewhat minimalistic and require a lot of cycles of setup compared to a VIA), one VIA is RAM bank and LCD only, one VIA is button input, IRQ input and timers (since it is the only chip connected directly to the 6502s IRQB pin, every other interrupt signal has to go through this VIA), one VIA is for expansion/GPIO (as already said, likely going to be PS2 keyboard input) and I have two ACIAs just becuase I already had them.. and if I only ever need one of these, I won't have another one lying on the shelf for the next couple decades...

so basically I use very inefficient function placement for the chips in order to have an excuse for cramping every 6502 related chip I have into one project so I finally have them sorted (if you understand what I mean ^^)

This looks really cool! Hoping I can get mine to this point one day. Where do you get that eeprom holder and does it allow you to program it without removing it from the board?

I think the possibilities are pretty interesting. Banking then becomes like a context switch each bank with its own direct page and stack and perhaps a simple way to implement multitasking. My instinct would be to go smaller or larger on the bank size (either 32k so you can swap between very large programs and applications) or much smaller to conserve memory.

The somewhat obscure MOS 6509 processor (not to be confused with Motorola 6809), banks out not just the bottom 16K but the entire 64K. The 6509 was featured in some of the Commodore CBM machines, so you might gain some insights by seeing how Commodore managed the situation.

-- Jeff

It would be a little easier than the MOS 6509 because if you are only swapping out the bottom 16K then at least you could implement a small kernel somewhere in the upper 48K without having to worry about banking out to ROM, or copying the ROM into every bank, as you would have had to have done on the 6509.

But probably still no walk in the park to fully exploit.

sorry for the late response...

these sockets are called ZIF (Zero Insertion Force) and are there to easily be able to swap out cips. Because during development I will have to reprogram the ROM very ofthen, I figured this would be justified. You can get them off ebay, mouser, amazon or whatnot

Synthron: congratulations, you've made a beautiful machine!

I am every curious about your memory layout and banking, as I am exploring similar issues. I've considered (very briefly) the consequences of swapping bottom RAM including the stack, and decided it's best to avoid doing so, if at all possible.

In my case, I wanted to make calls to the OS routines located in a separate 64K page. Not sharing the stack between mappings makes cross-page calls cumbersome, and in certain configurations nearly impossible.

How do you handle cross-page calls and returns when the stack is swapped out as well?

well, I decided to just try it... in worst-case, I'll have only just shy of 32k RAM, which is for my usage (just as a plaything and first Proof of Concept) more than enough. It certainly will be interesting
my thought was that every task will have its own 16k page, thus can have a seperate stack and ZP. Task-handling will likely be timer based, so on each timer interrupt, I'll push A, X,Y and State-Register as well as current address (if possible) to the stack, switch the bank and pull the last state out of it. not the most efficient design, maby a very DUMB design, but I wanted to give it a try... If that doesn't work, I can just swap out the Chip-Selects for the banked ram and the shared ram and have 16k shared lower ram (ZP and Stack included) and bank the upper 16k-ish ram. So best case I have a somewhat unusual working design, mid-case (swapping the chip selects) I have a sorta normal design, worst case I just have 32k-ish ram....

My GeckOS implements preemptive multitasking by re-mapping the memory in 4k blocks, with each task having at least its own 4k block for dedicated zeropage and stack.
Just if you want to have a look

(That would be good for a new thread...)