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Does anyone have any experience (or information) as to whether the W65C21S is suitable for operation in 3.3v circuits (with suitable downrating of the clock frequency)? My confusion stems from the following:

• The data sheet initially specifies a 5V supply with a tolerance of plus or minus 10%.
• Later in the data sheet the absolute maximum rating for Vdd ranges from -0.3V to 7.0V (but with no adjustment for propagation delay/maximum clock speeds at different frequencies).
• The parametric search at Mouser suggests that the S version has a supply voltage from 1.8V to 5V.

Background: By analogy with the W65C22, I would have expected the N version to be 5V and the S version to at least support operation at 3V at a lower frequency. Everything I've found for new builds at 3V use the 65C22, which is actually what I currently have in my design. However, most of its additional I/O features are wasted as I don't really need them, and I'm using clock-stretching to interface with a secondary microcontroller so the timers have very little use also. An old-school IO expander like the 6521 would be perfect for the circuit assuming the S-variant can actually function on a 3V supply.

Unfortunately WDC's data sheets have had a lot of problems, and sometimes we're on our own to experiment and find out what the truth is. With a quick look at the W65C21 data sheet (.pdf), I immediately saw quite a few very questionable things. The good part is that usually the parts are a lot better than the data sheets say. I do believe you'll find they'll work down to 1.8V or even lower, at reduced speeds of course. I think you'll also find that the pin drivers are extremely strong compared to what the W65C21 data sheet says, as is the case with the '22 and the '816, per my experiments.

I would still encourage using the '22 rather than the '21 though. I have not used the '20 or '21 in decades; but one thing I remember is that writing to their data-direction registers and then reading or writing to the ports, alternately, is very clumsy and inefficient compared to how the '22 does it. So why is that important? Take for example any case where you want to bit-bang a bidirectional synchronous serial port like I²C, 1-Wire, or PS/2, where essentially you want an open-drain I/O pin. On the '22, you can write a 0 to the output bit, then to pull it down, make that bit an output, or to make it a 1 or to read it, make it an input. Going back and forth between accessing the data direction registers and the accessing actual ports on the '20 or '21 takes a lot of steps. You have to tell it, "Ok, now I want to access the data-direction register," and then do it, and then "Now I want to access the port itself, and then do it. The '22 has separate addresses for those registers, so you don't have to make a separate announcement every time, which could be 16 times for a single byte!

A quick comment on this point: you feel the 65C22 VIA timers aren't much use in your case because their timekeeping would get distorted by the clock stretching, is that right? FWIW, here is a simple circuit which can clock-stretch the CPU without disturbing the timers in a VIA.

-- Jeff