6502.org

Hello,

I am new to hardware design and would like to design a 6502 SBC. I am now trying to design a memory mapper/decoder.
The memory layout I came up with is as follows

0000-BFFF = RAM
C000-CFFF = I/O
D000-FFFF = ROM

And the decoder (oututs active low for chip selects) Is that acceptable? Do you have any advice for how to improve it?

Your decoder would give you a shadow of the IO_range at E000-EFFF. You must also decode A13 to eliminate this shadow.

-RAM = AND(A14, A15) ;use NAND and invert output
-IO = NAND(-RAM, -A12, -A13) ;Invert A12, A13 at input
-ROM = NAND(-RAM,-IO)

I am pretty sure there is ways to simplify this and optimize usage of gates. Example using 8 2 input NANDs (2 ICs):

-RAM = NAND(1,NAND(A14,A15) ; 1= tie high
-IO = NAND(-RAM,NAND(1,NAND(NAND(1,A12),NAND(1,A13)))) ;1 = tie high
-ROM = NAND(-RAM,-IO)

or using 3 3 input NANDs and 3 NOTs (inverters) (2 ICs):

-RAM = NOT(NAND(1,A14,A15) ; 1= tie high
-IO = NAND(-RAM,NOT(A12),NOT(A13))
-ROM = NAND(1,-RAM,-IO) ; 1= tie high

One more thing I should mention: Writes to RAM must be qualified with phi2 as during -phi2 address lines are invalid and cause unintentional writes to invalid addresses. Read more here: http://wilsonminesco.com/6502primer/addr_decoding.html

Oops, I see it is defaulting to RAM. You might look at a 74xx138.
Dwight

For this job, the 74HC85 would be a good choice. It's a 4-bit comparator giving greater-than (ROM select), less-than (RAM select) and equality (I/O select) outputs. Tie the cascade inputs low, apply the A12-15 lines to the A input, and tie the B input to $C.

You'll then need to invert each output to produce the /CE signals needed by many devices; a hex inverter may be efficient for that, if you are using just one device to fill the 48KB RAM and 12KB ROM areas. Adding a 74HC00 to produce correct /OE and /WE signals is also standard practice. Don't forget to tie off unused inputs on these to GND or VCC; unused outputs should be left open.

As your memory map gives you a large 4KB area in which to put I/O devices, you may want to further decode that area by cascading one or two 74HC138s from the primary decoder. The '138 has three enable inputs, two active-low and one active-high, which can be used both as cascade inputs and to decode a fourth address line. To decode sixteen 256-byte blocks, invert the equality output of the '85 and feed it to /E1 on two '138s, and apply A8-10 to the address inputs of both. Then apply A11 to /E2 on one, and to E3 on the other; this will select one decoder in the high half of the range, and the other in the low half. Tie the remaining, spare enable on each '138 in the active state.

You can of course apply a second layer of '138 decoding to get 16-byte address blocks for each I/O device. But for a first homebrew board, this likely won't be necessary.