Commodore 64 address decoding

[Dan Moos]

Does any one know if a source for a detailed explanation of the Commodore 64's address decoding scheme? I'm ok if it treats the PLA as a black box, as long as it tells me what outputs a given set of inputs should produce. But it's also the glue logic I'm interested in. I've found a lot of info on the PLA, but nothing much else.

My recollection is that a single address is spread across all 8 chips or something, which is very much beyond my experience.

I'm repairing an old 64, and while I believe it's a bad PLA (sadly, my modern replacement not arriving for a week), I feel if I had a better grasp of the decoding details, I could make a more educated assessment.

[kc5tja]

The PLA is the only chip that does any kind of address decoding. The PLA equations contain all that's needed to know what chip receives its chip-select given the current address on the bus. The VIC-II chip is responsible for DRAM timing generation. And the 6510 processor has an I/O port built into it which is used to bank ROM and I/O in and out of the memory map. And the cartridge port has two more pins which are used (GAME and EXROM) by the PLA, but are not accessible by the software running on the machine. The PLA is the only chip I'm aware of that does the actual address decoding.

All the chips receive low-order address bits in common (e.g., the CIAs get A0-A3, the ROMs get A12-A0, etc.), since the specific select bit asserted at any given time is decided (via the PLA) by the upper address bits, the CPU's R/W, LORAM, HIRAM, and CHRGEN pins, and the cartridge port's GAME and EXROM pins.

[Dan Moos]

What are the two multiplexers for? there is also a 74139, and various other glue chips in the RAM portion of the board?

BTW, I got the thing going. Bad RAM

[White Flame]

Dan Moos wrote:

My recollection is that a single address is spread across all 8 chips or something, which is very much beyond my experience.

That's simply for models that use eight 64k x 1-bit RAM chips. Throw the address bus at all of them, and each drives 1 bit of the data bus. That really doesn't change any of the address decoding, though.

For individual mutiplexer roles, you can look at the schematics: http://www.zimmers.net/anonftp/pub/cbm/ ... index.html It seems the PLA doesn't necessarily generate chip select signals directly, but just which I/O region is active, then those chips demux the high address bits into individual chip select signals.