6502.org

Hi all!

This is my first post here, but I've been working and exploring about this topic for some time now. I'm trying to build a system that can interact with a 65xx CPU. Basically, my idea is to replace a 6526 in a Commodore computer, so I'm dealing with old NMOS technology, and it won't need to go higher than 2MHz.

To give you some background about myself, I have some good knowledge of digital circuits theory, I have no issues with boolean algebra, logic circuits, etc. However, I'm really lacking real world experience, where propagation delays are a thing, and timing has to be taken care of.

I think I've got the bus timings more or less right... and before I start building a small prototype for testing, (And who knows, maybe blow up my computer!) I'd like some advice from you experts.

To get the most basic test case, let's suppose I only have a 74377 8bit register (With a /E input, and positive edge triggered clock) to hold 1-byte value, and a 74244 tri-state buffer to output that same value to the data bus when requested. So, for this test circuit, I use PHI2, RW, /CS (Provided, in this case, by the C64 PLA) and the data bus as inputs. We can ignore the Address bus at the moment, as my little 8bit register will appear in the whole range this chip is selected by /CS.
I'm pretty confident about the "Write" portion of my schematic, although I have some doubts about inverting the PHI2 clock. I'm doing this as the 74377 write is triggered on a rising edge, but, the 6526 latches the input on the falling edge of phi2. By the time PHI2 falls, /CS, RW, and Data will be stable so, the positive edge of my inverted PHI2 will make the 74377 latch the value in the databus.

The "Read" portion also seems OK. When /CS is low, and RW is high, the 74244 will be enabled and its contents available in the databus, so the CPU can read the value at the falling edge of PHI2.

No matter how much I read (Documentation, Datasheets, forums), I find many different solutions and I feel the only way to be 100% will be to test it, but any previous advise... will be very much appreciated!

Cheers!

Welcome daniMolina!

I first thought your work wouldn't work, but the 377 works a little different than a 374 so, yes, it should work if /CS isn't too late.

I think a 541 is a replacement for a 244 with a little more friendly pinning. Don't forgaet p1 of either 244 or 541


Have fun!

Thanks! According to a 74HCT377 datasheet I intend to get, /E has to be low 18ns before the rising edge of the clock input. According to some timings I have for the C64... /CS and RW are setup for at least, 420ns, so plenty of time here..
Yep, you're right! Having 2 /OE pins on the 541 may save me a few logic gates. About p1... I spotted that after uploading the image

Cheers!

Hi daniMolina,
Some years ago I did an experimental TTL implementation of the 6522.

Maybe my old schematics contain some material useful for your project, maybe not, good luck.

Hi all,

I just wanted to tell you, that last night I've implemented that small 8 bit memory, exactly as per the schematic, and it works like a charm. I can write an 8 bit value to it, and read it. I've connected it to the expansion port of my C64 so... it seems I've got it right

Congratulations!

Yes, congratulations! Always a good feeling to set a goal and put what you've learned into practice.

Now is good time to look for possible refinements. You can eliminate one of the OR gates: the one that ensures /G of the '377 goes low only if /CS is low and /RW is low. Instead, it's alright to run /CS directly to /G of the '377. For the '377, /RW doesn't matter.

It may seem undesirable to allow the '377 to load even during a read cycle, but it's actually not a problem. That's because during reads the '244 will be driving existing data onto the bus. And reloading the existing data isn't a "problem" worth spending an OR gate to fix.

Right! Also... not blowing up my old C64!
Nice point. However, I'm not sure if I'll be able to save that OR gate in my final project. This was just a very basic test to check if I've got the bus timings and signals rights, but, in the end, reading and writing to a same register may not always return the same value. (I'm aiming to build a discrete logic 6526)

Now that I've managed to tap into the data bus... it's time to get into the address bus. Here's my next test.
I'm using A[0..3] along /CS (Connected to /I01 in the C64) with a 74138 so, my "address space" consist of 16 bytes, repeated along the whole I01 address space. ANDing the whole data bus with the reset line, will allow me to set the 377 register to all zeros whenever there's a reset. There may be better solutions for this (I'm sure there are!) but hey, I'm still in the Newbies sections of the forum

If this second test is successful, I'll start a new thread to track the progress of my 6526thing . Even though my main goal is to replace the 6526 in a C64, I also will test it with a modern 6502, to test how fast can I push it.

Congratulations.

Not to confuse you, but:
74377 is a bit exotic, and you already have noticed that clearing all of the registers at RESET won't be fun when using 74377 based registers.
So I just wanted to toss in an alternative approach for using 74273 chips as registers:
Looking forward to watching your progress, good luck.

All ideas are welcome, I'm waaaay out of my area of expertise here.

I considered using 273 when I was starting with this... but I wasn't able to find an adequate logic to enable the register write. I will give your idea a try. It really feels it will save a few gates. Fortunately, right now I don't think I'll have an issue with board size.

BTW, here's my first contraption :
I'm pretty proud of it... especially since I've also created the Expansion Port adapter, the SOIC to DIP adapters, soldered them myself (My first try at SMD soldering!) and it did work on the first run. Beginner's luck maybe?

Thanks for posting the picture.
Looks nice.

If you run into trouble with crosstalk between the wires in a ribbon cable when trying to run the design at a higher speed,
making every second wire GND (like with old floppy cables) will fix that problem.


IIRC both ports of the 6526 have open collector outputs.

After you got two registers working (a data register and a direction register),
please take a look at the datasheets of 74125 and 74126
// 74HC(T)125\126, 74AC(T)125\126 etc.
There might be other buffers (or logic gates with open collector output) that might look interesting too,
but when doing a search for them, better check first if they are available as 74AC\74ACT parts.

Second circuit also worked!
This has to be the more convoluted 8 bit memory built in the last 20 years.

Since now my work will focus on the 6526 recreation, I'm starting a post in the Hardware subforum to keep track of my project.

Cheers!

Second circuitry worked ?
Congratulations: it's the concept of how we do register write control in our 20MHz TTL CPU.

Downside of that circuitry is, that the LD signals from the address decoder now have to be HIGH_active.
Adding 7404 inverters to the outputs of a 74138 would be an option.
Another option would be using the (slightly exotic) 74240 8 Bit inverting buffer instead of the 7404,
which would simplify the PCB layout, but from the datasheets 74240 seems to be a little bit slower than the 7404.

74238 is a decoder similar to 74138, except that it has HIGH_active outputs.
But that chip seems to be a bit... exotic.

;---

Now some more words about the bus interface:

65816 puts A23..A16 on the data bus during PHI2 = 0,
to be fair to those who want to build a 65816 accelerator card for the C64,
maybe it would be better if the TTL 6526 doesn't drive the data bus during read cycles when PHI2 = 0.

In our TTL CPU, we had put 100 Ohm resistors into the lines between the 74AC\74ACT chips and the bus connectors for preventing the old NMOS chips in the C64 from getting damaged:
First: the drivers inside the old C64 NMOS chips can sink/source a lot less current than the new 74AC\74ACT chips.
Second: 74AC\74ACT gives out signals with _fast_ rising and falling edges, and maybe there is a bit too much energy in these edges to keep old NMOS chips healthy in the long run.
Third: When the C64 and the TTL CPU are running with two different power supplies, both power supplies usually are not switched on\off at the same moment.
;
Because we ran out of PCB space, we had to use individual resistors, but I should mention there are
resistor networks in DIP16 package which contain 8 individual resistors.
(When using them, don't solder them into the PCB directly, but have them plugged into precision DIP sockets instead,
just in case it becomes necessary to tinker with the resistor values... during debugging, maybe).

Also, we had decided not to use SMD chips for signals that go into the CPU, but chips in DIP packages instead,
(plugged into precision DIP sockets) so one could resort to chips from different logic families:
74ACT is fast, and has a ca. 1.3V logic level threshold (TTL compatible). But because of this, it's sensitive to "dirt" on the bus lines.
74AC is fast, when powered with a +5V supply it has a 2.5V logic level threshold. As in "still fast, less sensitive to dirt, but probably won't work with a C64".
74HCT is slow, and has a ca. 1.3V logic level threshold (TTL compatible). //That's your first choice if 74ACT gives you trouble.
74HC is slow, when powered with a +5V supply it has a 2.5V logic level threshold. //Safe, but slow, probably won't work with a C64.
//Logic level threshold is the "turning point" which seperates the logic LOW from a logic HIGH at the input pin of a logic gate.
The list above contains CMOS chips only. In "case of emergency", 74ALS245 also makes a nice bus driver.

Hmm... a lot of capacitance slows down a bus, and IC pins tend to have some capacitance
which sums up when a lot of chips are tied to the same bus.
For this reason, it would be better to have buffers between the bus and the address decoders etc.

Using two different 8 Bit data busses inside the TTL 6526 (one for read, one for write) is a good idea,
because it simplifies the math for the timing a lot when aiming for speed... at the cost of a more complicated PCB layout.
One bidirectional databus (for read and write) inside the TTL6526 would simplify PCB layout,
at the cost of making the math for the timing a lot more complicated... please DON'T do that.

;---

Two threads.
I'm now getting confused about where to post my stuff...
let's just put the experiments in this thread, and the implementation of the "end product" in that other thread ?

That's some big pile of useful info.

For now I'm sticking with HCT parts. I may have been a bit impatient and I ordered an assortment of ICs some time ago For sure they'll work at 1MHZ, and I think they can go up a bit, (Probably not higher than 10MHz?) But enough to get me started.

About the two bus design, I kinda came up to it naturally, it felt easier to handle than a single bidirectional one. Good to know it's easier in higher speeds.

I intend to leave this thread as it's now and follow up with all work in the hardware forum. I find it tidier that way. This thread purpose was for me to get a grasp on the basics of the bus.

Cheers!