6502.org

Going forward, I see the 6502 scaling into designs with millions of cores, acting as a simple parallel X/Y register vector processor...
in addition to a ultra-low-latency single-core high clocked serial processor for funny mainframes running extremely linear code. (some transaction/fax/credit card processing machines?)

https://www.realworldtech.com/forum/?th ... tid=175275
^Final plan to execute and manufacture the 1486 with short lead time while cutting unnecessary costs to the absolute bone (distributed BOINC validation may be an option for some parts of the logic, offering discounts to those that can prove they participated). Competition in the near future might include: NVIDIA Denver, Intel Itanium III, IBM POWER, souped-up VAX, various SPARC, Mill VISC 'racetrack dynarec'. The #1 advantage of the C-1486 is of course the 99% market dominance of x86 in desktops and laptops, with the extreme flexibility of the architecture allowing it to scale from tiny die to 900mm^2 16-core ones, combined with the native x86 CISC execution, removing the advantage of running JIT x86 emulation from these other processors. Price will be $500,000 or more initially. All x86 OS from MS-DOS 1.0 to Windows 10 to Linux to OS X to BSD will be supported if possible.

(The 1486 can be microcode hacked to run a 6502/6510/65xx system. GPIO and serial ports can be used for I/O.)

Also, AMD K12 (but I would love to work with them rather than against them, and I think they would stand to gain)

And finally, a souped-up AMD K10 (Phenom III?) perhaps made by Russian government agencies.

Any comment?

6502 > "graphing processor"

Erm... I can't make sense of this post....
Also, you might be better off posting on the AnyCPU.org forums. That site has a much broader scope.

It reminds me of this topic: "idea: a cell-like chip based on many 6502 cores." Unfortunately a couple of the most knowledgeable posters there seldom drop in here on this forum anymore. I have a couple hundred old 2MHz 65c02's and 65c22's, and nearly that many 8Kx8 EPROMs, and I have long thought it would be fun to get some small boards made up to experiment with an array of processors, partly to learn how to program for this kind of thing.

Michael J. Mahon has done some significant experimentation along similar lines, and has been very polite and generous to me in the past. If his work piques your interest, drop him an e-mail and see if he'll share what he has been doing lately.

Mike B.

Indeed, Michael Mahon's work with NadaNet and his AppleCrate machines is well worth study. In fact it's the usual story: study the history of what's been tried and how it's turned out, and you'll benefit from the experience of others.

For many cores, memory bandwidth is the issue, as noted rather early in the cell-like thread: how many cores you can fit is not so important as how many cores you can feed. Note that modern multi core chips have a huge area devoted to cache (area is the resource that matters, not transistor count.) You can feed more cores if you have small memory needs and great locality - the transputer model is one of local memory, not a single shared memory. (See also this pipedream thread.) And then you just need to solve the problem of factoring your problem into thousands of programs.