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Blog post series on Creating a C64 system on FPGA
Posted: Thu Nov 16, 2017 5:20 pm
by fastgear
Hi All
I have started a blog series on creating a C64 system on an FPGA.
Here is the link:
http://c64onfpga.blogspot.co.za/2017/11 ... ction.html
Will keep you posted on new posts.
Re: Blog post series on Creating a C64 system on FPGA
Posted: Thu Nov 16, 2017 5:59 pm
by BigEd
Subscribed!
Re: Blog post series on Creating a C64 system on FPGA
Posted: Fri Nov 17, 2017 5:16 am
by MicroCoreLabs
Looks like a cool project. Good Luck! You might consider adapting my MCL65 core which has passed all of the tests you described and was used to power a Commodore VIC-20, Atari-2600, and an Apple II+.
http://www.microcorelabs.com/mcl65.html
Re: Blog post series on Creating a C64 system on FPGA
Posted: Fri Nov 17, 2017 3:04 pm
by fastgear
Just published my next post. In this one I have decided to linger a bit on some Verilog basics, just to get everyone aboard:
http://c64onfpga.blogspot.co.za/2017/11 ... asics.html
Re: Blog post series on Creating a C64 system on FPGA
Posted: Sat Nov 18, 2017 11:38 pm
by Fatsie
Link for
FPGA implementation of a C64 by Peter Wendrich.
T65 is another 6502 core; it's VHDL though. I'm using it for my Retro-uC and have a fork on
my gitlab.
Re: Blog post series on Creating a C64 system on FPGA
Posted: Sun Nov 19, 2017 1:17 pm
by fastgear
Hi Fatsie.
Thanks for the links. Very interesting project indeed.
One thing I am just curious about Wenrich's fpga implementation is that he mentions that the latest version he cannot release the source code because it contains source code from the Chameleon project.
Any idea what this project is about?
Re: Blog post series on Creating a C64 system on FPGA
Posted: Sun Nov 19, 2017 1:45 pm
by Cray Ze
Turbo Chameleon 64 is an Altera EP3C25 FPGA along with RAM, crammed into a C64 cartridge.
It was originally a VGA output cartridge, but was so overpowered that many other features came along.
It can run standalone without being connected to a C64, it can even run an Amiga core.
Lots'a'links.
https://icomp.de/shop-icomp/en/produkt- ... on_64.html
http://www.syntiac.com/chameleon.html
http://wiki.icomp.de/wiki/Chameleon
https://www.c64-wiki.com/wiki/Turbo_Chameleon_64
And a video of it being an Amiga.
https://www.youtube.com/watch?v=kb-iT2LkrLs
Re: Blog post series on Creating a C64 system on FPGA
Posted: Mon Nov 20, 2017 3:17 pm
by jac_goudsmit
Interesting!
I may have to port that to one of my FPGA boards (I have several of them because I maintain the P1V Virtual Propeller project on Github). I never had a C64
===Jac
Re: Blog post series on Creating a C64 system on FPGA
Posted: Mon Nov 20, 2017 4:53 pm
by fastgear
The Turbo Chameleon sounds like an awesome device.
The only thing is it looks like the fpga design can only be used on altera fpga's because of some functional blocks incorporated in a binary.
Re: Blog post series on Creating a C64 system on FPGA
Posted: Mon Nov 20, 2017 5:14 pm
by Cray Ze
Which sources are you looking at? As far as I'm aware, Turbo Chameleon is closed source.
The original FPGA64 project ran on a Xilinx Spartan-3
First paragraph on this page "History".
http://www.syntiac.com/c_one.html
Re: Blog post series on Creating a C64 system on FPGA
Posted: Mon Nov 20, 2017 5:54 pm
by fastgear
I was following the following link from fatsie:
http://www.syntiac.com/fpga64.html.
Newest version of fpga is only binary because it contains chamelon sources
Re: Blog post series on Creating a C64 system on FPGA
Posted: Tue Nov 21, 2017 2:55 pm
by fastgear
Re: Blog post series on Creating a C64 system on FPGA
Posted: Sun Nov 26, 2017 3:34 pm
by fastgear
Just released my next post in the series:
http://c64onfpga.blogspot.co.za/2017/11 ... -fpga.html
In this post we develep the FPGA implementation capable of running the Test Suite.
Re: Blog post series on Creating a C64 system on FPGA
Posted: Wed Dec 13, 2017 12:07 pm
by fastgear
Re: Blog post series on Creating a C64 system on FPGA
Posted: Wed Dec 13, 2017 12:42 pm
by Cray Ze
Just watch out that casex doesn't bite you in the ****.
It's designed to match on an UNKNOWN condition, and can lead to problems in the synthesized design that never show up in simulation.
This paper give a good explanation of the issues with casex (page 9).
http://www.lcdm-eng.com/papers/snug99_rtl_coding.pdf