6502.org

Hi, my name is Ralf and I am from Germany. My first contact with homebrew microprozessor was building an 8-bit breadboard computer using the tutorial from Ben Eater on youtube. I am totally happy that my conditional jump (if Register A is zero) works.
Now I want to get into the 6502. Step 1 would be to get LEDs connected to the addresslines blinking while the 6502 is doing hard wired NOP's. What do I need to get started? Is it possible to have a clock speed of only 1 per second?
I have: High quality breadboard, LEDs, resistors, capacitors, wiring cable, some 74LS Gates, arduino nano,

I would buy:
1 x 65c02 from mouser.de
What else do I need?

PS: Yes! I will now read the primer link

edit: typo

The W65C02S can be stopped indefinitely in either phase without losing the data in its internal registers. So yes, you can have a 1Hz clock.

If you use an instruction like LDA #$A9, (which is A9 A9 and takes two cycles for the whole two-byte instruction), you can have the address advance by one with every cycle, unlike the NOP.

Welcome!

I do not recommend using 74LS gates with the CMOS 65C02. Instead, I suggest you use the 74AC or 74HC equivalents.

Ah yes, I missed that the first time. (You'll run into it in the 6502 primer though.) Dump LS. Its only advantage is that it is not easily damaged by static discharge. You'll have other static-sensitive parts you'll have to work with anyway though, so that advantage is basically lost. Use CMOS logic. LS's biggest disadvantage is that it can hardly pull up to a valid logic '1' for CMOS parts that have to receive the signal. Its inputs also cause heavier bus loading. In most cases (but not all), 74HC is slightly faster than 74LS. 74AC is much faster; but it's fast edge rates run a little more risk of running into AC behavior problems for newbie construction.

And of course, welcome!

Thanks for your replies and your welcome. When I started a couple of weeks ago I knew barely nothing.
I was wondering why there are so many different NAND and NORs. I realised that the AHCT ist often cheaper than the LS Version and that the "T" would help with TTL circuits. But the advise with HCT instead of AHCT is very useful. I ran into some strange behaviour when I built the 8bit breadboard computer. I solved this by using a "bigger" power supply (2A USB Charger) and I bought 100nF capacitors for every IC.

So, as I have managed to get the 65C02 in free run mode (using the LDA as proposed) I'll certainly come back to ask the next questions.
Now I am reading the PRIMER tutorial. Hopefully I'll find there where to connect my clock

One thing to note about the HCT/ACT parts is that the 'T' only affects the inputs. Those are made to accept TTL input levels, but the internal logic and the outputs are the same.

The clock signal goes to pin 37 on the DIP. It's labelled PHI2 in the datasheet.

Yes, as DerTrueForce said, the "T" in "HCT," "ACT," etc. means TTL input levels. The processor though, and maybe other parts, specify minimum logic '1' input voltage of 70% of VDD, which at 5V means 3.5V, and if there's any LS feeding it it, the HCT parts will do fine but the processor is not guaranteed to. Pulling out an old National Semiconductor data book for 74LS, I'm seeing that they're not guaranteed to put out more than 2.7V for a logic high. That's a far cry from the needed 3.5V.

It should be noted that some cases 74ACT/74HCT logic is slower that the equivalents without the "T". For first time builds, however, this difference can be ignored.

Ben Eater's breadboard computer series on YouTube is excellent, so you should have no problem transitioning to 6502 projects.

Yes! This series helped me a lot. I always wanted to understand why 0 and 1s are sufficient
But I must say the Primer Tutorial is excellent! It answers all the questions I had. It's not a video but the kids from my generation learned to read!

The second idea (besides 6502 free run) is to connect a "WDCW65C51N CMOS Asynchronous Communications Interface Adapter" to the breadboard computer. Just to learn (by practice) how this works.
Simple start could be: instead of sending the data to the output registry - send it to a PC with terminal program. I have no clue how this works. But I know there will be a "LOGIC" explanation.

Currently I try to fill my mouser basket to get the 50 Euro minimum amount (not to pay shipping costs)

lg
Ralf

One extremely unfortunate thing about the 65c51 ACIA is that it has a few bugs in it. The biggest one is that the bit in the status register that tells you when it's finished sending a byte is stuck as a 1, which indicates that it's ready for another byte. The interrupt system is also broken in a similar manner. The only way around that bug is to use a delay, that is, have the 65c02 wait for a certain number of cycles, so it doesn't corrupt the outgoing data.

If you're clocking it by hand, then you should be fine, but if you're using an oscillator, you need to use a delay. The ideal solution is to use a serial chip that isn't broken, but every other UART that I've looked at (that you can get new) seems to be more complicated.

The W65C51 has a bug in even parity. But who uses parity? Otherwise the transmit-register-empty-flag bug is the only one in the '51. You don't have to use a delay loop though if you have a 65(c)22 VIA and can spare to use one of its timers. Set it up for one-shot interrupt for the right amount of delay and re-start the count every time you write to the '51. Then the processor can do something else useful while waiting for the next time the transmit register can be given another byte, and get the cue from a timer interrupt.

I kind of wish a couple of the ACIA's functions had been separated; but until the above bug showed up in the last version, I never had any problem with the '51. I've been using it for decades, and every attempt has worked on first try. Nevertheless, I will probably use the MAX3100 14-pin UART which is interfaced through SPI for the next build.

I got the UART from BBD UART paper for my first SBC build, but I am still distracted by Jac's excellent L-STAR and learning spin and prop asm. So can't comment if, as a newbie, the UART is easier to get working than the 65c51.

You are going to need some RAM. The 6502 needs RAM from address 0 to 0FFh and for subroutines from 100h to 1FFh.
8K byte static RAM are common. That would be enough to do quite a bit with.
You also nee some place to store non-volitile memory.
You have several options here. Most use EPROMs but this has the disadvantage
that you need a programmer.
You can use battery backed CMOS memory. You can use a static RAM and build
you own circuit or use a Dallas NVRAM that has a 10year battery built in.
These are nice because they can be treated like a normal RAM to write to them.
Since there is always the potential while experimenting that you might have
a run-away program, you might want to have a switch on the write control.
Another option is to use a EEPROM. These need no battery but the writing
needs to be done in a more algorithmical method as these are slower than
RAM for writing. These would be fine once you have some other NVRAM such
as EPROM or battery backed but these would be harder to bootstrap by toggling
in a program.
You'll need some method of address decoding for the different blocks. Chips
such as the '138 and '139 come in handy here.
You'll also need a bootstrap method to initialize the NVRAM. It would most likely
need to be switches and someway to stop the 65C02 while accessing the NVRAM.
I recommend putting the NVRAM at the high memory as the 65C02 needs its
reset vector at the high end of the 64K address space.
I hope this help you a little on getting started.
Dwight

Although this is perfectly correct conventionally, it's also true that an application might use very little RAM - just 128 bytes in the Atari 2600 which was mapped into both those areas, so you had stack at the top and zero page at the bottom, and it was up to you not to let them overlap. That's even enough RAM to contain a small program too.

I mention this not to be pedantic, but because it's an important moment when we realise what it means to partially decode addresses and to have chips appear at more than one location.