6502.org

Hi,

I'm looking at the Addressing Modes in Western Design Centers w65c02s manual and noticing that the addressing modes have clock cycles beside each of the steps taken during the address mode.

For example,

Under Zero Page Indexed X:

Clock Cycle. Contents of Address Bus, Contents of Data Bus
1. PC, OpCode
2. PC + 1, zp
3. PC + 1, IO
4. 0,zp+X, AAL
5. 0,zp+X+1, AAH
6. AA, Data

Now this addressing mode is used for several instructions, for this example, AND. And AND takes up 4 cycles under this addressing mode.

My question is: Does this mean that the total number of cycles needed to execute an AND instruction is 6 + 4 =10?

Andrew
AND

I'm not exactly sure which addressing mode you're referring to. AND ZP,X takes only 4 clocks. AND (ZP,X) takes 6. No 6502 instruction ever takes more than 7. It's probably best to write the addressing modes this way since "indirect indexed" and "indexed indirect" get so confusing. The notation AND (ZP,X) and AND (ZP),Y make it more clear if the indexing comes before or after the indirection.

Sorry, I meant Zero Page Indirect (zp,X).

But your response never answered the question either.

According to the documentation the addressing mode takes six cycles to obtain the absolute address (and data) that AND will work with.

Doesn't this mean that it will take an additional six cycles to perform the acutal AND'ing of the data?

> Sorry, I meant Zero Page Indirect (zp,X).

Now I think you mean Zero Page indexed indirect, like AND (ZP,X), which takes six clocks.


> Doesn't this mean that it will take an additional six
> cycles to perform the acutal AND'ing of the data?

No, that happens in one clock while it's fetching the next op code, so it's not extra.

We'll I copied it right out of the manual so I'm pretty sure I meant Zero Page Indirect (zp,X).
So what about the more complex instructions? Does this mean that all instructions only take one clock cycle (the last one)?

> so I'm pretty sure I meant Zero Page Indirect (zp,X).

The ,X or ,Y always mean it's indexed. The parentheses always mean indirect. In this case it's both, and and the ,X before the ) means the indexing takes place before the indirection is carried out.

> So what about the more complex instructions? Does this mean
> that all instructions only take one clock cycle (the last one)?

The longest ones are indexed read-modify-write instructions like incrementing, decrementing, rotating, or shifting of a non-ZP memory location, and where the indexing makes it cross a page boundary. Those are 7 clocks. (These instructions don't offer indirect addressing modes.) Nothing takes more than 7 clocks regardless of how you count them. In the case of a write to memory, it has to use the bus to do so, so it can't do that while fetching the next op code at the same time. This means the entire operation will be done in the 7 clocks (or less), instead of finishing up while fetching the next op code.

The instruction execution rate is not constant and will depend on what you're doing of course; but for a rule of thumb, you can figure that MIPS will be about 1/4 the MHz rate. So while the instructions take anywhere from 2 to 7 clocks, the average in actual program execution is about 4. If your program does a lot of ZP operations and little or no indexing and indirection, the average will be a little less. If you do lots of indexing and indirection, it will be a little more.