6502.org

Ok, my parts are slowly trickling in. Mouser stuff should be here tomorrow, and that should complete my current hardware orders

Much reading has been happening as I wait, and of course, this means more questions!

I found the original MOS 6500 Family Hardware Manual here on this site. That one seems like a gold mine! Relatively easy reading too as far as these things go.

Anyway, since I ordered a modern CMOS chip from WDC, I'm assuming that the timing stuff (like data has to be stable for x ns ) are gonna be different, right? I know I need to read the actual datasheet for the part I ordered, but those are rarely as clear as that MOS document was.

With all the CMOS stuff I ordered, including 74HC logic, I'm fine running everything at 5 volts, right? I only ask because in my reading, I always see 5v ascribed to TTL, and 3.3v to CMOS. Yet all my MCU projects have been 5v, including some 74HC shift registers. So now I'm confused. Would the statement "CMOS stuff (at least this stuff) is good for 3.3, but is 5v tolerant? Is there a document out there somewhere that sorts this out?

Address decoding. Okay, I just want to make sure I have what I need. I will have a 32k RAM and 32k ROM chip. I am fine leaving portions of either inaccessible in an early prototype just to get things going. I am lead to believe that with a single VIA, single ACIA, and the memory chips I mentioned, a single quad NAND can do it. I also see mention of people using 3 to 8 decoders. I have 1 74HC00 on hand, and 1 74HC138 (along with others. I ordered a kit with 31 specimens). I also have a quad Schmidt trigger NAND. That is as good as the 74HC00 in this case, right? No ill can come of the Schmidt trigger inputs I assume, right? I also have a Hex inverter, and a quad AND, which basically gives me another (slower) quad NAND.

All this to ask, am I sufficiently stocked here? I ordered 2 VIAs and 2 ACIAs, and I can imagine wanting to use all of that eventually. But like I said, I'm willing to have a more crippled version at first.

I have noticed (i think) on YouTube, some builders seem to have dedicated crystal oscillators for their ACIA and I think their VIA. I could totally be wrong here, so maybe its not what I saw. I ordered 4 1 MHz oscillators, and 4 2 MHz oscillators. Am I okay here?

I also ordered some used books:

6502 Assembly Language Programing by Lance Leventhal

Programming nd Interfacing the 6502: With Experiments by Marvin De Jong (I am particularly liking the sound of this one)

Programming the 6502 by Rodnay Zaks.

Any obvious books that I should be getting? I know there are .pdfs out there, but I love old tech books (and new).

I think that's it for now. Thanks for being patient with my questions!

WDC's is much, much faster, and the times will be shorter. Do get the WDC data sheet.
yes

WDC parts can go much faster at 5V than 3.3V, but you're not pushing the speed limits either way; so you wouldn't need to do 5V unless you need 74HCT or 74ACT logic. The HC and AC can work fine at 3.3V but will be slower. Their preferred voltage is 5V. 74HCT and ACT are 5V only, and there are other CMOS families that are made to work at 5V, like most 74LVC. They're not just 5V-tolerant. They actually use a 5V supply and put out 5V (or very close to it for a logic-high output.
The '138 is much slower; but at the speeds I think you said you're going to be going, it won't matter.
It's slower than the '00 non-Schmitt-trigger counterpart, but again, at your speeds, it won't matter. The Schmitt-trigger quad NAND leaves one gate left over to use in your reset circuit if you like, eliminating the need for other active parts to get a clean reset signal.
You'll use the 1 or 2MHz for the processor and system clock. The VIA's and ACIA's Φ2 input signal comes from the same place as the processor's. Don't use separate oscillators. The only extra oscillator you need is for the ACIA's baud-rate generator which is separate from the system clock. 1.8432MHz is the normal frequency for that.
All 65xx programmers should have the excellent programming manual, "Programming the 65816 including the 6502, 65C02, and 65802" by David Eyes and Ron Liechty. This is a .pdf file of a rather large book that is well laid out and is much better than the description there lets on. Note: There were many problems with the earlier .pdf version that were not in the original paper manual; but in late March 2015, WDC scanned and OCR'ed the paper manual and posted the new, repaired .pdf. It's not just an outstanding, very complete manual; it covers the extra CMOS instructions and addressing modes which I don't think your books above do. To see the many improvements of the CMOS 65c02 over the NMOS 6502, see my article at http://wilsonminesco.com/NMOS-CMOSdif/ . The only good reason to stick with NMOS is if you're going to be programming old home computers that used only the NMOS, like the Commodore 64 whose 6510 (which is a 6502 with a parallel port stuck on it that it uses for memory management) was never available in CMOS. For new builds, I would always encourage going with CMOS, for the many reasons given in the article.

Of the above three, the only one I would consider worth purchasing would be Dr. Leventhal's book. However, the first edition of that tome is some 40 years old, so keep that in mind as you read. The WDC programming manual that Garth mentioned should be your primary reference for getting familiar with the 6502 assembly language.

Ok, all makes sense.

Am I to understand that I will for sure want a 1.8432 MHz Oscillator for my ACIA's baud rate generator? And this should be an actual oscillator can, not just a crystal, right? Also, if I wanted 2 UARTS for some reason, can the same oscillator serve both?

The answers are in the last half of the page of the 6502 primer, http://wilsonminesco.com/6502primer/IO_ICs.html .

Ah! I've at least skimmed that entire document, and this isn't the first time its been shown I missed the answer to my own question. Oscillators ordered!

I'm having difficulty knowing where to look for a good monitor/assembler. I just want to be able to look at memory, and assemble simple "prove it works" code. Basically the bare minimum.

Actually, I'm not really clear what the minimum code (if any) that a ROM needs to have for the machine to be in a "normal" state on power on.

The 6551 requires a 1.8432 MHz clock to generate the "standard" data rates, where "standard" means the ones described in the data sheet. I recommend an actual oscillator, as it will guarantee operation.

The same oscillator can drive more than one 6551. However, if you eventually decide you want two or more serial ports there are better ways to achieve them. Keep in mind that the 6551's technology is very dated, the device originally appearing c. 1977. UARTs have greatly improved since then. Unfortunately, the WDC 65C51 is completely unchanged from the old NMOS part, other than being CMOS and able to operate at higher bus speeds. Plus it has a "stuck bit" problem that has caused several users of the device around here some grief.

While on the subject of the 6551 and other 65xx bus-compatible peripherals, all of them require that Ø2 be connected to them, this being the same Ø2 that clocks the microprocessor (MPU). The 6521, 6522 and 6551 understand the 6502 bus cycle and "know" that the rise and fall of Ø2 indicates when the data bus is valid and when it isn't. It is imperative the chip selects and RWB of these devices be valid before the rise of Ø2—it is implied that RWB of each of those devices must be directly connected to RWB on the MPU. Your glue logic that is selecting a 6521, 6522 or 6551 MUST NOT be gated by Ø2, a common practice of amateur 6502 circuit designers.

In the case of the 6522, the Ø2 clock is also the reference for the two timers and the serial shift register, which is somewhat unfortunate, since changing the Ø2 frequency changes the rate at which the timers run. As an example, if you write some code that is depending on the timer(s) to generate a jiffy IRQ at, say, 10 millisecond intervals for timekeeping purposes (a 100 Hz IRQ), you have to load the timer latches with a value that represents the number of Ø2 cycles that will elapse in 10 milliseconds. If you subsequently change the Ø2 frequency, your timing "assumptions" will be wrong and you will have to change your code to suit.

The exceptions to that last paragraph are that the VIA's T2 can be made to count pulses on PB6 instead of Φ2, and the shift register can be made to use T2 or an external shift clock. (Just beware of the bug of mode 011, shifting in under control of an external shift clock. A flipflop is needed to get around it. See my post and diagrams in "Tip of the Day," #8, at viewtopic.php?p=2310#p2310 .)

For a design that might increase clock speeds over the coming years but want to keep using the same software, a frequency counter could be made with T1 and T2 of a VIA. T2 would count pulses on PB6 from a reference frequency that would not change over the years, and T1 would interrupt after so many Φ2 counts and the ISR would see what count PB6 had gotten to (or, since you only have to do it once, use a loop in the reset routine instead of using an interrupt), and calculate what the Φ2 frequency is and put it in a variable for any subroutine that needs to figure out what values to use to keep constant timing in spite of improving Φ2 clock rates.

The Zaks book is very readable. Although it covers the 6502 only, not the 65C02 - at least not my version, an early one. Not a bad choice at all. The Leventhal book is fine too, but the Zaks book was the clincher to get me into the 6502 back in the day. I actually read through it again a couple of years ago - it's a pleasure to read.

As you ordered a new WDC 65C51 ACIA, I strongly suggest you read this thread, otherwise, it's highly unlikely you'll manage to get that part working: viewtopic.php?f=4&t=2543

Also, if you prefer not to deal with the defective Xmit feature, you can always get an old Rockwell R65C51P4 chip, which will function properly.

Just a note... my 65C02 CPU board uses 32KB RAM, 32KB EEPROM, a 74HC30, 74HC00 and 74HC138. I use Page $FE for I/O and have been running at 10MHz for a couple years without issue. Memory parts are rated at 70ns for RAM and 150ns for ROM, but apparently the Atmel 28C256 is conservatively rated. I also have the ability to write the EEPROM insitu which works fine.

Best of luck in getting your initial board working... needless to say, there's lots of expert help out here

Well, that is a surprise, and no mistake. When I did the calculations on that part(from the values in the datasheet), I found that it would limit me to about 4 MHz. I would call that excessively conservative, unless you've got a mislabelled 28HC256 from the same company. I'll have to try that on my own board, once I get the UART working.

My SBC-2 OS has a disassembler (65C02 opcodes supported) and mini-assembler (like the Apple]['s) and can support Xmodem file transfers. You can also get EhBASIC if you want to play with it. It's not hard to set it up with you IO map and has drivers for 6551's.

You can read more here and I'm happy to help tailor it to fit your needs.

More info here -> http://sbc.rictor.org/sbcos.html

Daryl

I don't think it's a mislabeled chip, unless the entire tube of 10 were mislabeled. I've used about 3 or 4 of them in the 10MHz clocked board set. The board set is all WDC chips (65C02, 65C22, 65C51). I did get a few different lot number W65C51 chips from WDC a couple years ago. One works at higher speeds without issue. It does require a can oscillator however, so I've also used a 3.6864MHz and am running at 38.4K baud on the chip.

I built 3 board sets (Express PCB mini-board service of 3 PCBs). The other two are limited to 4MHz as the R65C51P4 ACIA won't run any faster than 4MHz. I use the slower boards for long term testing and the fast set for development. If you up the clock on your setup, do post if you have any issues.

Daryl, that sounds good. I'll look it up for sure when the time comes.

I am aware of the bug in the 65c51. I will likely order the Rockwell part, but still might try some of the work arounds. We'll see. My wife has started to notice the steady trickle of parts, so...

I'm starting to connect my data bus. As I am on a breadboard, I wanted a tidy way to wire it. I happened I have tons of that colored ribbon cable, and a well stocked kit for making .1" breadboard connectors, so I'm making custom length 8 pin ribbon cables for my buses. So far, it is looking really clean, and my bus lines will have a consistent color code.

I'm running the data bus from the CPU to a central area on the breadboard. From there an individual ribbon cable will run to each chip. I will do something similar with the address bus.

My immediate goal is to get the buses complete, the clock going, and the reset circuit going.

About the reset. Any pointers for a simple, timed and debounced circuit with jelly bean parts?

http://wilsonminesco.com/6502primer/RSTreqs.html