6502.org

It appears that a2heaven.com is working on a 6502 compatible plug in board to replace a 6502/65c02 cpu with a 65816. Not available yet, but it looks like it's in the pipeline...

https://www.facebook.com/a2heaven/photo ... =3&theater

Like the 65802, can address only 64k but can switch to native mode for 16 bit registers, relocatable stack and direct page.

Cheers,
Andy

Of all the places information about something like this device could be posted, why on Facebook?

From the post:

• 65C816->6502 board
  Advantage :
  - use 8 and 16 bit instructions set
  - full pin to pin compatible
  - generate missing PH1 and PH2 signals
  - generate SYNC signal
  - keep data bus in high impedance during PH1
  - low power consumption
  - up to 14Mhz

Concerning that highlighted item, the real 65C802 did not high-Z the data bus during Ø2 low, which is also true of other 65xx devices. I don't understand why this device would do such a thing. Any system that wanted to claim the data bus during Ø2 low would have the necessary hardware already in place.

Also, what is an "8 and 16 bit instructions set"?

I found the link to the facebook page at a2central.com. There's another website a2heaven.com with other products. It looks a lot like a project I've seen proposed here using a 65816 as a pin-compatible replacement for a 6502. I would think that since a 65816 emits a bank address on the data bus that's the reason for the high impedance so as not to interfere with an apple IIc's video cycle (perhaps). 8 and 16 bit instruction set is probably another way of saying emulation and native mode. The folks are located in Bulgaria I believe. English isn't their native language.

Cheers!
Andy

That might have been the thinking, but the 65C02 shipped with the Apple ][c did not have that characteristic, nor did the 65C802. Generally speaking, the 65C family stays on the buses at all times unless the BE input is driven low, at which time A0-A15, D0-D7 and RWB go to the high-Z state.
Except there is no such a thing as an eight and 16 bit instruction set, and the instruction set has no relation to operating mode. The m and x bits in the status register determine if a load, store or implied register operation (e.g., INX) operates on eight or 16 bits, but the actual instructions are the same in either case.

It's important to understand that all 65C816 and 65C802 instructions are valid in both modes, although with some limitations in emulation mode. For example, SEP works in both modes, but the m and x bits cannot be changed while in emulation mode, preventing the selection of 16 bit registers. Certain instructions, such as TCD and TSC implicitly operate on 16 bits regardless of operating mode. Also, the B-accumulator remains accessible in emulation mode through the XBA instruction.

It can be said that in emulation mode, 65C816 sort of becomes a 65C02 in terms of software, but almost looks like an NMOS 6502 to other devices on the buses, except the bank bits are emitted during Ø2 low. In terms of software, the real 65C802 was the same as the 65C816 in emulation mode, but accurately produced the 65C02's bus characteristics.

Agreed. And both of those CPU's "float" the data bus to its high-impedance state when Phase2 is low -- right? You seemed to say otherwise in your previous post, but I'm not 100% sure I understand the wording used. My take on the '802, 'C02 and 6502 datasheets I've seen is that the bus floats.

But the '816 is exceptional in this regard because when Phase2 is low its data bus presents the bank address. That could present a problem in the context of an '816 used for a 6502 compatible plug in board, but evidently they've managed to deal with that. (I want one of those boards! )

WDC's 65c02 data sheet's timing diagram implies that if you have two write cycles in a row like you would when pushing a return address onto the stack, the processor may continue to assert the data bus through phase 1 but with data that's not guaranteed to be valid between the end of tDHW and tMDS.

That's the sort of thing which would have me suspecting the datasheet!
(Could you clip a snapshot and post it?)

I suppose that as with so many other things regarding WDC data, you just have to try it if you want to find out.

Thanks for the clip! (If you want to test if a bus is driven or not, you need to sprinkle some resistors around.)

Certainly the diagram above is thought-provoking. The portion Garth circled seems to show the data bus driven to an invalid state. If the bus were invalid because it's floating then you'd expect it to be drawn as show below, using the usual visual vocabulary. So, can we conclude the bus is driven?
I don't believe so. We know that BE floats the bus. Why isn't its behavior drawn in the expected fashion (below)?

I think maybe the draftsman was a new hire! The diagram is flawed, IMO. But if there's other evidence to say a 65c02 (or any 65xx processor other than the '816) can drive the data bus in phase 1 then I'm all ears.

That, or check the driver's seat to see if anyone is occupying it.

Even more interesting and confusing was the timing diagram from the 65C832 data sheet:
The "dead time" signal state is shown as "flat lined," which I would interpret to mean the 65C832 has floated the relevant outputs.

On the other hand, the 65C816 timing diagram uses yet another "notation" for some of the signals during the clock cycle "dead time":
Well, we all know WDC's documentation leaves something to be desired. So guess we shouldn't be too surprised over these anomalies.

I happened to locate a datasheet for the 65802/816 from 1991. Perhaps helpful...
Cheers,
Andy

Good find.