6502 bus buffering
Posted: Wed Apr 28, 2004 4:08 pm
Hi,
I'm half way through designing and building a simple 6502 based expandable SBC for use as a general purpose controller.
The basic system consists of a 160x100 eurocard with a 6502 clocked at 2MHz, 1x 8K SRAM (6264), 1x 8K EPROM (2764), 6522 VIA and not much else apart from glue logic. Pretty basic as it goes. It already runs up on breadboard without too much hassle.
One small problem is that the system needs to be expandable and therefore I need to take the bus off the board (via a R/A DIN41612 connector). At worst case, there are going to be bus runs of about 20cm and up to 5 additional 6264 SRAMs and 4 6522 VIAs running off this bus.
Will this run without buffering stably, if not; what is the best way to buffer the data, address and clock lines? Also, should I buffer the bus on the CPU card or all cards?
Cheers all.
I'm half way through designing and building a simple 6502 based expandable SBC for use as a general purpose controller.
The basic system consists of a 160x100 eurocard with a 6502 clocked at 2MHz, 1x 8K SRAM (6264), 1x 8K EPROM (2764), 6522 VIA and not much else apart from glue logic. Pretty basic as it goes. It already runs up on breadboard without too much hassle.
One small problem is that the system needs to be expandable and therefore I need to take the bus off the board (via a R/A DIN41612 connector). At worst case, there are going to be bus runs of about 20cm and up to 5 additional 6264 SRAMs and 4 6522 VIAs running off this bus.
Will this run without buffering stably, if not; what is the best way to buffer the data, address and clock lines? Also, should I buffer the bus on the CPU card or all cards?
Cheers all.