6502.org

Maybe this has been addressed before, but my search efforts didn't turn up anything relevant.

The VIC-II chip uses a multiplexed arrangement to access the address bus. What is a good and simple way to demultiplex that bus? I was thinking along the lines of using some kind of IC, but I don't know what it's called. One set of address lines is timed off the CAS signal, the other off the RAS signal.

My thinking is if this chip was timed to the one signal, latches the value, and holds it, then the next address set is presented, and that gets latched and held, presenting a full demultiplexed address.

The RAM I am using does not use the RAS and CAS signals, it expects a full address to be presented at once.

'374 should do the trick. If RAS&CAS have the wrong polarity you can throw in an inverter.

Perfect. That's what I was looking for.

The Commodore 64 uses a 74LS373 octal latch.
You control the latch gate with RAS/ and the 3-state outputs with AEC/

Looking at that actually makes a little more sense. I do need the address to be bi-directional. Just so long as the output holds that state till it is released.

I'll have to take a close look later. But from initial appearances that looks good.

It looks like octal latches might be what I need for other parts of my project.

FYI, 74xx573 has the same function as 74xx373 but the '573 pinout is rearranged in a way that's usually better for PCB layout. Similarly, '374 and '574 are the same except the '574 has an improved pinout.

You'll definitely need one '373/'374/'573/'574 to demultiplex the Row Address but I doubt you'll require another to demux the Column Address. You could include another anyway -- it'll do no harm -- but you don't need it.

The muxed bus presents one half of the address then the other. The first half (the row) MUST be latched because it's about to disappear. And the latch output feeds half of the RAM address inputs. But when the second half of the address (the column) appears on the muxed bus it will remain, isn't that right? (The VIC-II timing diagram will tell you.)

I'm suggesting the muxed address bus from the VIC can directly attach to the other half of the RAM address inputs. Your RAM won't be instructed to do anything (ie; no WE or OE) until after CAS has gone true -- right? By that time both halves of the address entering the RAM will be stable.

For this application I'd lean toward using a latch, BTW -- ie '373/'573. I think that's a slightly better choice than a '374/'574.

Sounds right. I'd have to check the timing. It should work. I am leaning towards the latch. The other might work, but I don't think it's as good a choice. The octal latch seems to almost be purpose made for what I'm doing.

I'm curious...are you building a SBC that uses pieces from a C64?

The preservationist in me hopes you are not gutting C64's for this.

Either way, sounds like an interesting project.

Only dead C64s.

If you run short on them let me know. I acquired a stack of them from an ebay seller when I bought something unrelated. They've already been stripped of any socketed parts. I have no real use for them but I'm not ready to pitch them yet.