6502.org

I've recently gotten interested in the 6800 processor. Has anyone ever used one in a project?

I haven't used one yet, but from reading the books, I see several nice features:
- Tri-state address bus. With a 6502, to do any sort of "DMA" activity, you'll have to use separate tri-state buffers, since the 6502 is *always* putting out an address. Which brings up a point: the 6502 hardware manual says several times that the 6800's "Valid Memory Address" signal is not needed, because the 6502 is *always* outputting a "valid" address. I think the MOS people were stretching the truth a little... when more than one signal is involved, there is *always* a time when things are indeterminant. Also, note that 6502 designs generally gate the address-decode with the clock, so in effect, a VMA signal is being generated by external hardware anyway. The 6800 does it internally.
- Richer instruction set than 6502. It may be that some of them are not too useful, but the 6800 has a more complete set of instructions, I think.
- The 6800 descendants are still very popular, and I believe can execute 6800 instructions (like the 68HC11).
- A wider variety of peripheral chips were made for the 6800.
- A 16-bit Stack Pointer. You can put the stack anywhere in memory, and it can grow as large as you want!
- A 16-bit index register. You can use an indexed addressing mode across all of memory!
- A separate vector for Software Interrupt (SWI) - so the 6800 has a total of 4 vectors in the top of memory. The 6502 shares the BRK vector with IRQ.
- A 'HALT' signal, which causes the CPU to stop and release the buses and the R/W line, so that another device can take over the bus (like for DMA). The halt can also be done in software - there is a Wait For Interrupt instruction, where the 6800 releases the bus until an interrupt occurs.

Some 6800 down-sides:
- Requires a 2-phase non-overlapping clock, like the 6501 did. This clock is not really TTL - the spec says that it must go to close to Vcc level. I think this is easily achieved with an open-collector driver, though. Note that the 6501 is pin-compatible with the 6800 -- MOS intended that you could plug it in, change the software, and it would work.
- When it was new, the 6800 cost 3 times as much as a 6502; but of course that's irrelevant now... Both are just a few bucks each.
- The 6800 takes more time to do certain things than a 6502 does.

It seems that the 650x was, at the time, a good low-cost alternative to the 6800. MOS dropped some instructions that probably weren't used much, simplified some things, etc. But here in the 21st century, for home-brew experimenting and such, the 6800 looks like a lot of fun.

Pete

...And I forgot to mention that the 6800 has 2 8-bit accumulators, which makes up for having only one index register (although it's 16-bit - yay!). The follow-on CPUs to the 6800, such as the 6803, added instructions for combining the two accumulators into a single 16-bit accumulator, thus allowing some 16-bit math to be done. Cool!

Another interesting chip is the 68008, which is a 68000 with 8-bit data paths. So you can run 68000 SW with 8-bit-wide memory and I/O.

And, for a high-performance 8-bit CPU, the 6809 was hard to beat...

Pete

> I've recently gotten interested in the 6800 processor. Has

> anyone ever used one in a project?

Uh-oh! Uh-oh! The gauntlet has been thrown down and now I must defend my friend the 6502!

In his book "65816/65802 Assembly-Language Programming", author Michael Fischer says, "The 6800 was designed on a shoestring budget. The 6800 came out in February 1974 and was based on the architecture of the then relatively popular PDP-8 minicomputer. It was designed as a compromise between a controller and a general-purpose processor, which resulted in an instruction set that was not especially useful for either application. Later in 1974, eight people who had been involved in the development of the 6800 left Motorola and went to work for MOS Technology..." They built on what they had learned at Mot, and the 6502 was out a year later.

Comparing the old 6800 and 6502 in their original versions is not terribly relevant if you want to know what you can do with them today. Both families have evolved, and I don't think there's any reason to use the slow, instruction-strapped original versions when the newer ones are so much nicer.

> I haven't used one yet, but from reading the books, I see several
> nice features:
> Tri-state address bus. With a 6502, to do any sort of "DMA"
> activity, you'll have to use separed tristate buffers...

The 65816 has a BE (bus enable) pin (pin 40 of the PLCC) for that. [Edit: The W65c02 does too-- pin 36 of the DIP.] It also has VDA (valid data address) and VPA (valid program address) outputs, plus ML (memory lock) to ensure the integrity of read-modify-write instructions in a system where something else also has access to the same memory, ant VP (vector pull) to indicate that a vector location is being addressed during an interrupt sequence. This signal may be used to select and prioritize interrupts from several sources by modifying the vector address.

> Richer instruction set than 6502. It may be that some of them are
> not too useful, but the 6800 has a more complete set of
> instructions, I think.

The 6800 has 197 op codes compared to 65c02's 202. Admittedly, the 02's 32 op codes for BBS, BBR, RMB, and SMB have the bit number built into the op code itself and not into the operand, which may make the op code list look artificially high. But the 65c02 has more than twice as many addressing modes as the 6800 (15 versus 6). The 65816 has 24 addressing modes, and 255 op codes (without the BBR etc above), and one reserved for future expansion with 2-byte op codes.

Comparing any two families of processors, you're likely to find a nice thing or two about one that's not on the other. I've designed PIC microcontrollers into a few products, partly because they're easily available off the shelf with a lot of I/O options, and we can program them ourselves easily. The microprocessor at the heart of a PIC has a couple of instructions that would be nice to have on the 6502; but generally, I hate the PIC's uP. It's extremely clumsy, and takes twice as many instructions and twice as many clock cycles to do a job as the 65c02 would take, if the PIC can do it at all.

> The 6800 descendants are still very popular, and I believe can
> execute 6800 instructions (like 68HC11).

True. Both families have evolved. There definitely are more microcontroller choices in 68 than in 65, by a long shot. On the other hand, the performance of the modern 65's is generally beyond that of the 68's.

> A wider variety of peripheral chips were made for the 6800.

Is that true? The 65's offered the

• 6520
• 6521 PIA
• 6522 VIA
• 6523 TPI
• 6524 PIAT
• 6525 TPI
• 6526 CIA
• 6529 single-port interface (20-pin)
• 6530 RAM, I/O, and Timer
• 6532 RAM, I/O, and Timer
• 6545 CRTC
• 6551 ACIA
• 6552 dual ACIA
• 6560 VIC (NTSC)
• 6561 VIC (PALB)
• 6567 VIC (NTSC)
• 6569 VIC (PALB) text
• 6572 VIC (PALN)
• 6573 VIC (PALM)
• 6582 SID
• 5710 FDC
• 8722 MMU
• 8360 Text-Editing Device
• +other 8000-series that were directly 6502-compatible

(This list does not include the 20 or so 6502 variations like the 6508, or the 65-family microcontrollers, like the 65F11.)

Unfortunately, most of these creatures have gone extinct. Of those, even if you can still find some, they won't work at the faster clock speeds that the modern 65c02 can run. Again, there are many more 68-family modern microcontroller variations available off the shelf.

> - A 16-bit stack pointer. You can put the stack anywhere in memory,
> and it can grow as large as you want!

The 65816 has a 16-bit stack pointer. Its stack-relative addressing modes make it much more efficient to work with parameters passed from routine to routine by way of the stack.

> - 16-bit index register. You can use an indexed addressing mode
> across all of memory!

Again, the 65816 has two 16-bit index registers. You can also use them in 8-bit mode. The index register mode, 8- or 16-bit, is selected through bit 4 of the status register.

> - A separate vector for Software Interrupt (SWI) - so the 6800 has
> a total of 4 vectors in the top of memory. Th 6502 shares the BRK
> vector with IRQ.

The 65816 has a separate BRK vector, and adds the COProcessor and abort interrupt vectors.

> - A 'HALT' signal, which causes the CPU to stop and release the
> buses and the R/W line, so that another device can take over the
> bus (like for DMA). The halt can also be done in software - there
> is a Wait For Interrupt instruction, where the 6800 releases the
> bus until an interrupt occurs.

In addition to the BE input, the 65816 has the SToP and WAIt instructions. I had in mind that although WDC's 65c02 does not have the BE, it does have STP and WAI-- but I can't find that information right now. I've never used them myself.

> Some 6800 down-sides:
> - Requires a 2-phase non-overlapping clock, like the 6501 did.
> This clock is not really TTL - the spec says that it must go to
> close to Vcc level. I think this is easily achieved with an open-
> collector driver, though.

The 6501 was a closer knock-off of the 6800, and Mot sued MOS over it. In an out-of-court settlement, MOS quit making the 6501 and came up with the improved 6502.

Using 74HCxx or 74ACxx parts, the high logic state is really pulled up very close to 5V without the heavy speed and power penalties of going to open-collector.

> When it was new, the 6800 cost 3 times as much as a 6502; but of
> course that's irrelevant now... Both are just a few bucks each.

The 65816 is only about a dollar more than the '02 also. I believe the microcontroller versions of both families however can get up into the $20-$30 range. At the low end of the range, the 68-based microcontrollers are much cheaper.

[I tried to edit this, and Delphi cut it off before the end; so it finishes up in 137.10.]

As you pointed out right up front, it's easier to compare the modern versions of each... I agree, but then I must point out that many of your counter-points are 6800 vs 65816, not 68HCxxx vs 65816.
I think of the 6502 and 6800 as 'historic', and I was comparing them as such. I'll do a more detailed comparison of 6800 vs 6502 opcodes, to see if I was all wet in thinking that the 6800 was more flexible.

Some of the 65xx parts you listed are unfamiliar to me, and I assume that some of them were never produced in quantity (??). I think that in, say, 1976 or so; the 6800 had a better selection.

Pete

> I agree, but then I must point out that many of your counter-points
> are 6800 vs 65816, not 68HCxxx vs 65816.

Yeah, I was thinking I should edit the last part to clarify that I think you'll find the '816 more exciting than anything now in the 68xx family of microprocessors. Again, if you want a microcontroller, there's definitely more to choose from in the 68's. The only '816-based microcontroller I know of that's available off the shelf is the 65265. It's a very nice product, but there are no user-programmable versions, whether based on EPROM, flash, or anything else. You can connect external ROM, but then you lose the I/O use of many of the pins. Because of your post, I guess I'll leave my other one unedited so others can see what you were responding to.

> I'll do a more detailed comparison of 6800 vs 6502 opcodes, to see
> if I was all wet in thinking that the 6800 was more flexible.

Do compare WDC's 65c02 though, instead of the old NMOS version which had some serious bugs and fewer instructions and addressing modes. Earlier, Rockwell, and now WDC, have the direct bit-manipulation instructions. I don't think CMD's have them, and I think Mitsubishi (who is not very interested in selling to you and me) does have them. Although they have (or had) the extra things like STZ, JMP(addr,X), BIT#, ADC(ZP), etc, many of the brands did not have the direct bit-manipulation instructions. All brands of 65c02's have the NMOS bugs fixed, like JMP(XXFF) and invalid flags after a decimal arithmetic operation. The 65c02 has no minimum clock speed, and WDC's can be stopped indefinitely in either phase, not just phase-2-up. My first 65c02 computer only took a couple of milliamps to run (at 130kHz to hold power consumption down).

> Some of the 65xx parts you listed are unfamiliar to me, and I
> assume that some of them were never produced in quantity (??). I
> think that in, say, 1976 or so; the 6800 had a better selection.

I don't have any quantity information, but apparently most of these were readily available in the mid 80's when I called Commodore about parts for something we designed at work, and they sent this huge packet of data sheets and brochures, obviously hoping we'd buy a gillion. Some others were not made by Commodore-- Rockwell's 65c52 dual ACIA comes to mind.

Garth

I did a little checking this morning.

First let me start by saying that I'm looking at the original 6502 vs the original 6800. It's safe to say that in later generations of both, the features improved quickly. As I mentioned before, I have a 'historical' interest in this stuff, not necessarily a 'practical' interest. I enjoy building old-fashioned stuff using vintage parts - it would be "cheating" to use a modern CPU.

I think my offhand impression stated in 137.1 was correct: the 6800 has an overall richer instruction set:

The 6502 has 56 instructions; 6800 has 72.
The 6502 has 146 opcodes; 6800 has 197.

As for addressing modes, these need some 'interpretation'. I think the old MOS literature has some exaggerated marketing hype.

6502 lists addressing modes as follows (left column), with the 6800 equivalent on the right:
Now for the interpretation:
To me, the four indexed modes of the 6502 are all 1 mode (or 2 at most). Clearly, abs,X and abs,Y are not separate "addressing modes".
The 6800 doesn't have the indirect modes. BUT, having a 16-bit index register makes up for this in most cases. And, the 6800 has a version of indexed that is sort of like: OPC 0,X , where the "0" is implied - that is, the 16-bit X register contains the address of the operand.

At first glance, the 6502 appears to have much cooler functionality with all the variations on indexing and indirection. BUT, the value of a 16-bit index should not be underestimated. And, it's conceptually simpler, too. So, the 6502 would seem better for manipulating small tables (less than 1 page); but the 6800 does a better job with larger tables.
The 6800's "0,X" indexing is very useful - it's simply a 16-bit calculated address. With the 6502, you must always have a "hard-coded" operand somewhere. 6502 folks typically work around this by poking a 3-byte instruction into a known place in RAM, then jumping to it.

Pete

I don't have a 6800 programming manual, just the data book. Instruction set advantages and disadvantages I see are as follows.

6800 has an add without carry-- nice, but doing CLC before the add on the 6502 only takes 1 byte and 2 clocks. The mid-range PICs ONLY have add without carry, not with, and that's REALLY a pain!

6800 has CLR like 65c02's STZ. On 6502, you have to do LDA #0 then STA. If X or Y is not holding valuable data at the time, you might use one of them instead. It's an extra pain if you wanted to save all 3, A, X, and Y, but there's less of a penalty if you're clearing several memory bytes at once, since the LD* #0 only needs to take place once.

6800 has instructions to clear accumulator, but they're no faster than LDA #0.

6800's 1's complement memory instruction is kind of nice. The ones for accumulators save 1 program byte but no clock cycles compared to EOR #FF.

6800's decrement memory and decrement accumulator instructions, like many of its instructions, are considered separate instructions, whereas 6502 counts them as the same instruction with different addressing modes.

If you say 6502's indexed,X and indexed,Y are really the same addressing mode, I think you would have to say that many of 6800's separately listed accumulator instructions (for A and B) are really the same instruction.

6800's SBA (subtract accumulators) looks kind of nice, as there have been a few times it would have been nice if I could go A-X on 6502 without having to STX first. It's rare though. PIC uses M-A (they call it memory minus W, or Working register) instead of A-M. It really makes things much more difficult in most cases. The 6502 and 6800 way makes more sense.

6800's accumulator-test instructions are similar to 6502 CMP#0, which takes one more program byte but no more clocks.

6800's TST (test memory) does what the 6502 does automatically when you load the memory byte with LD*. 6502 requires losing the old data in the register to do this, but you can get the same test results by loading A, X, or Y, one of which will often be ok to overwrite. I use RAM bytes as flags, and test only the high bit. This can be done with the 6502 BIT instruction the same as I'd use the 6800's TST.

6800's INS and DES (increment stack pointer and decrement stack pointer) look cool, but I don't remember ever having any use for them. The 65816's stack-relative addressing comes to mind. It allows much easier access to different things on the stack.

6800's BSR (relative branch to subroutine) sounds cool, but the subroutine you need to go to is usually out of reach for a relative branch anyway. What you can do for longer relative branches on either processor (which is not necessary on the '816) is to put the branch offset in a memory location, then JSR to a relative-branch-long routine. This routine knows where you just came from because the JSR put the return address on the stack, and it adds the offset you just put in memory-- inefficient, but does the job. (Let it not be said that relocatable code is impossible on the 6502 or 6800-- it's just impractical. [Edit, years later: After trying it, I have to say that since it's extremely impractical to also relocate the data on these, being able to relocate the program is pretty meaningless.])

Some of the 6800's conditional branch instructions seem either trivial or redundant. I do remember times that it could have saved a 2-byte, 2-clock instruction to have something like BLE (branch if less than or equal); but overall, I think the 6502 more than compensates for those times by having a lower average clock-per-instruction count, higher clock rates, and two index registers whose 8 bits are virtually always adequate.

6800 has the BRA instruction (Branch Relative Always) which I missed on the 6502 until I was introduced to the 65c02. In my initial days of hand-assembly, it was a pain to have to change the JMP addresses every time I realized I had to insert an instruction here or there. For the short jumps, the work-around was to set or clear a status-register flag that wasn't being used at the time (usually V), then do BVC or BVS. Now with assemblers, I only use BRA to save a byte. If I really want relocatable code, I'll use the '816.

Not having the indirect modes on the 6800, you'd have to do more operations every time you need an indirect-indexed or indexed-indirect instruction, wouldn't you? I'd like to see Ragsdale's 6800 Forth kernel to compare the 6502 one, because Forth requires a constant stream of instructions using these addressing modes. His 6800 kernel was about 80% as fast at a given clock rate (20,000 primitives per second at 2MHz versus 25,000 for 6502), but I don't know any details.

> So, the 6502 would seem better for manipulating small tables (less
> than 1 page); but the 6800 does a better job with larger tables

If you were comparing arrays or strings, moving memory, etc., the lack of both a second index register and indexed-indirect addressing would mean a lot of extra motions between loop iterations, wouldn't it, defeating the hoped-for efficiency gain? The first 6502 Forth kernel I worked with used a CMOVE (character move) that was not limited to 256 bytes at a time. Being able to handle thousands of bytes at a time, the routine was kind of a long mess considering I have never needed such long strings; so I made it much shorter, simpler, and faster. With the 65816's block move instruction, this was a non-issue, so I went back to the 64K length limit in my '816 Forth.

> The 6800's "0,X" indexing is very useful-- it's simply a 16-bit
> calculated address. With the 6502, you must always have a "hard-
> coded" operand. 6502 folks typically work around this by poking a
> 3-byte instruction into a known place in RAM then jumping to it.

I've never needed to write 6502 code that writes code to jump to, with the single questionable exception of the double indirection in threaded Forth's inner loop NEXT . The 6809 offers a way that really cuts the instruction count, but not the cycle count.

Since the 0,X (with 16-bit X) addressing mode amounts to an indirect and not an indexed mode (since X will always be added to 0), a 6502 technique you could compare, if I understand what you're thinking of, is to use pairs of bytes in ZP as index registers-- gobs of them if you wish, and use X to select which index register you'll use next. So for example, if you had five 2KB tables and had to add or EOR (or whatever) the 1st elements of all the tables together and put the result in the 1st element of yet another table, and so on, you would have six addresses in ZP. These addresses would get incremented or adjusted as you go, and X would point to which one you're going to access next. To speed it up, you could leave these addresses alone for 256 iterations and a time, and just increment Y (taking 2 clocks per iteration) and incrementing the high byte of each address every 256th loop iteration. (You can't do both the X option and the Y option at the same time in one instruction though.) The effect is that of getting lots of 6800-style index registers in a 6502 program.

Going through this thought-provoking excercise has definitely sharpened my awareness of the differences between the two processors, as well as their pros and cons. I don't see how anyone can say the 6502 was a near knock-off of the 6800. They might be related; but in my family, I and my siblings don't look alike at all...[Message truncated by Delphi]

I think I agree with pretty much everything you said in .7.
You make a good point about the value of indirect addressing as an alternative (superior?) to a 16-bit index register.

Perhaps one convenience of the 6800 is that you could also store 2-byte vectors in RAM; then when you need to increment the pointer, you load it into X (I think that's done with 1 instruction??), then you can INC X, which is a 16-bit INC -- with the 6502, you need a couple of extra instructions to INC a 2-byte value.

I still like the 3-state address bus and the VMA signal of the 6800, though!

Pete

[This is a continuation of my original response 137.3, since I tried to edit it later and Delphi truncated it because of the length]

> ...And I forgot to mention that the 6800 has 2 8-bit accumulators,
> which makes up for having only one index register... The follow-on
> CPUs to the 6800, such as the 6803, added instructions for
> combining the two accumulators into a single 16-bit accumulator,
> thus allowing some 16-bit math to be done. Cool!

The 65816 also has accumulators A and B, if you separate them into 8-bitters. Accumulator C refers to the 16-bit combination if you elect the 16-bit accumulator mode (through bit 5 of the status register). Everything it can do in 8-bit-accumulator mode can also be done in 16-bit with no added complexity-- usually taking just one extra clock because of the added memory byte access. For example, ORA # in 16-bit takes three clocks compared to two in 8-bit.

> Another interesting chip is the 68008, which is a 68000 with 8-bit
> data paths. So you can run 68000 SW with 8-bit-wide memory and I/O

The 68000's interrupt latency at 8MHz is 21.75 microseconds, almost as long as the 8086. Compare that to 1.25 microseconds for the 6502 at the same clock rate. (This includes time to finish an average-length instruction executing when the interrupt hits. The actual interrupt sequence is a little shorter.) This info is from benchmarks on WDC's website.

Especially if you're already familiar with the 6502, I would encourage you to look closer into the 65816. Unfamiliarity may make it seem scary, but while you're learning the new features, you could just use it like a 6502 in a purely 8-bit mode if you wanted to. You could also use a few pin-header jumpers to make a board that will accommodate either processor, the '02 or the '816.

> I still like the 3-state address bus and the VMA signal of the 6800, though!

WDC's 65c02 has the 3-state bus (controlled by the BE pin). It does not have VMA, but it does have VP\ (pin 1 of the DIP) and ML\ (pin 5 of the DIP). The 65816 has VPA (valid program address) and VDA (valid data address) pins.

Garth

[ I meant to reply this to "ALL", but I couldn't find a way to do that... If someone knows how to modify this reply to be 'ALL', then please do so. ]

I recently finished my first 6800-based project. It's a vintage-style microcomputer, with the following features:
- 6800 running at 1 Mhz.
- S-100 bus.
- A "switches and lights" front panel (like an old Altair or IMSAI) with an interface to the S-100. The switches are from a DEC PDP-8i (made in the late '60's), and the LEDs are vintage, too.
- 8 KB of RAM on an S-100 card.
- 2 serial ports, and 16 bits of parallel I/O, using an S-100 card.
- I used late-70's vintage parts whereever possible.

So, the parts that I made from scratch are the CPU card, and the front panel interface, which is about 14 chips.

Now I'm playing with the 68701, which is a 6801 with 2 KB of EPROM in the same package.

I can definitely say that I like the 6800 better than the 6502, even though the 6502 was my favorite for almost 20 years... There's no substitute for 16-bit stack and index regs, and instructions to swap them around in various ways.

Pete