6502.org

In 1983 the UK magazine Wireless World published a computer kit project followed by three articles about the Forth language. It's a 6809 machine and was intended to run Forth, although I don't suppose there's anything very Forth-specific about the hardware - it has 8k ROM and 16k to 48k of RAM. The author, Brian Woodroffe, does have a quick look at available CPUs and picks the 6809 as being a particularly good fit - it can do a fast NEXT. See the bottom of the third page of the first article and the top of the sixth. In fact, let me paste it here: The articles are available as a set of PDFs at the bottom of this page:
http://vintagecomputers.site90.net/mags/ww/index.htm

The ones on the Forth language are:
Forth Language Part 1 October 1983.
Forth Language Part 2 November 1983.
Forth Language Part 3 December 1983.

IMO, the 6809 is the Mercedes of 8-bitters. But, I prefer to drive my Toyota (6502) ... it doesn't distract me with all the complex amenities I don't really need for getting from point A to point B quickly and economically.

Mike B.

It's hard for Forth folk not to be tempted by a chip with four very powerful index registers (stack pointers). Also I have no objection to distractions such as indirect and auto-increment/decrement address modes that collapse multiple assembly-source lines into one. Sure, there are some minor warts on the 6809, such as dead cycles and the inferior-to-65xx flag behavior, but the biggest problem -- as jmp(FFFA) noted in another thread -- is simply that it's not being manufactured in a fast, modern process. In fact, 6809 and 6309 aren't being manufactured at all, AFAIK. Thank goodness there are some soft cores out there -- including Rob Finch's RFT6809.

The assembly listing for Fig Forth for 6809 can be found here -- unfortunately just a scan, not something your assembler can accept, but illuminating for humans to peruse!

Speaking of assemblers, Brad Rodriguez discusses a 6809 assembler written in Forth here and here.

-- Jeff

Thanks for the mention Jeff. The 6809's one of my favs. The RTF6809 has a handful of additional addressing modes over the 6809. It supports a 32 bit address space in a manner akin to the 6502's support of a 16 bit address space with eight bit registers, using indirect addressing and zero page memory. In order for FORTH to be implemented using the 32 bit address space the NEXT routine and others would be coded more like they would on the 6502. Not nearly as fast as the 16 bit 6809 version, which is the cost of addressing of 32 bits.
32 bit next on RTF6809 It occurs to me that using 32 bit Forth words is really too much overkill. It would be better to use 16 bit words somehow extended to 32 bits if needed.
I'm wondering how to create a control branch for 16 or 32 bit words.

I agree about overkill. Another option is to use 16 bit words (and a 16-bit space) for the code (mostly Forth's lists of pointers or tokens), but have data default to 32 bit. IOW always allot 32 (never 16) bits for every item on stack. Now it becomes easy to bandy about "far" addresses that access the full address space.

Maybe I'm not explaining it well but I know the scheme is workable because I have 32-bit Forth for Real-Mode x86 that works that way! What a pleasure to simply @ and ! directly into the full address space (1 MByte in this case). But the tokens are small and the NEXT is fast. I suppose it might be described as a compromise, but I'm never gonna need more than 64K of code anyway. In contrast, removing the ceiling for data space really opens up new possibilities.

any advantage using the CMOS HD6309 versions? also, (with apologies for going off-topic) Chris Burke's "The 6309 Book" (262 page pdf, below) may be an interesting read...

Thanks, Michael -- it's good to have a reference like that, since the manufacturer (Hitachi) chose not to document the 6309's most powerful features. I don't know enough about them to answer your question, but it's certainly plausible that those features could be used to good advantage. But the physical package still only has 16 address lines, so there's no direct support for a larger address space.

Rob, back to the code space thing -- you & I discussed a related idea last year in your thread, 24-bit CFA ?. But I'm not sure it's worth rolling into your RFT6809.

Oh Jeff, surely you're ignoring the rather excellent HCS08 and HCS12 processors from NXP (nee Freescale; Motorola) which can reach speeds of 50MHz with many instructions hitting single cycles (e.g., TAX and INCx). The S12 is so close to the 6809 but so much faster with fractional and extended multiply and divide routines built-in or even weirder instructions like WAV (calculates the weighted average) and TBL (table lookup and interpolate). The S08 is slimmed down, but still faster than the old 6809 ever was by at least a couple orders of magnitude. And if that's not fast enough IPextreme can make chips using the S08 core at speeds up to 200MHz.

I'll be sure to check them out. Thanks for the tip!
Yup -- no doubt about it. I couldn't agree more.

Welcome! (oops, I see you're NOT new here -- merely silent until now. Belated welcome anyway, and thanks for speaking up)

The 68HC12 seems to have addressed my concerns with the original 6809 regarding machine code orthogonality ... the D, S, X and Y registers are all treated as machine code "equals", with no extra "byte-baggage" for the Y register instructions. It's a pity that they had to get rid of the U register to pull it off cleanly, though. All in all, I think that it's a very nice little unit, with lots of extra goodies. I'm sure that it would be a joy to program in assembly language, but it would take me a while to get used to all of the "new" instructions ... it would be a shame to go into a coding project with a 6809 mentality and miss some cool optimizations.

Mike B.

At first I had difficulty locating HCS12 doc; but, with that problem solved, I'm starting to get acquainted. It does seem that this family offers some good, Forth-y features! Like the 6809, it's very fluent with stack operations. The Address Modes (below) include pre- and post-increment and pre- and post-decrement modes that let you include a push or pop as part of another operation. On a slightly different topic, it's interesting that, "The CPU12 allows the index register to be incremented or decremented by any integer value in the ranges –8 through –1 or 1 through 8. The value need not be related to the size of the operand for the current instruction."

NXP offers a very wide selection of devices, most featuring a 16-bit data bus, it seems, and some with mapping logic that expands memory beyond 64K. But, as I eventually learned, HCS12 doesn't appear in the part numbers. A search on Mouser's site for HCS12 returns a bunch of MC9S12 part numbers, for example. There are lots of branches on the family tree, and I've only scratched the surface. The diagrams below came from the S12CPUV2 Reference Manual. Thanks again, nonarkitten, for the tip.

-- Jeff

But the '12 has only one stack pointer whereas the 6809 has two. Doesn't that make a big difference, even though the rest of the registers are as for the 6809.
Edit: I see that Mike B. already mentioned the missing stack pointer.

Because auto-increment/decrement address modes are available X and Y are highly effective as stack pointers. So, one could argue that the 6809 has FOUR stack pointers (X,Y,U,S) and the HCS12 has THREE -- which is still plenty!

ETA: I have to say, I like the idea of a quasi-6809 that runs at 50 MHz... especially when attached to a 16-bit data bus!

My interest is also piqued by "fractional and extended multiply and divide routines built-in or even weirder instructions like WAV (calculates the weighted average) and TBL (table lookup and interpolate)." WAV (weighted average) is one of four fuzzy logic instructions featured.