6502.org

Okay, here's an interesting hardware cunundrum for y'all.

The 65C02 and 65C815 data sheets both indicate that the MPU inputs respond to CMOS levels. So you would think that driving an input from a TTL device would not work—the TTL device wouldn't be able to pull up the input to the required minimum voltage, which is VDD × 0.8 according to the 65C816 data sheet. However, the 65C02 and 65C802 were designed to be drop-in replacements for the NMOS 6502. The NMOS part was used with TTL logic, which means that in order for the 65C02 or 65C802 to work as a replacement they would have to have TTL-compatible inputs a la 74ACT or 74HCT logic. This, of course, doesn't agree with what the data sheets are saying.

More puzzlement: the data sheet for the Cypress CY7C1049D 512kb × 8 static RAM says that it generates TTL levels on its outputs. This is also true for the ISSI 128kb × 8 SRAM I use in POC V1. Garth uses the CY7C1049D in his 4 MB DIMM and Daryl Richter has successfully used that DIMM in one of his SBC units (SBC-3, I think), operating at a relatively high Ø2 rate. All three of the POC V1 units I have built work without a hitch at 12.5 MHz. In fact, at boot time a detailed checkerboard test is conducted on all addressable RAM, and the system will halt and report an error if any location fails the test. Clearly the SRAM has to be able to adequately drive the data bus in order for memory testing to succeed.

So what is going on here? I find it difficult to believe that we've been unbelievably lucky and nothing has malfunctioned because the sun, moon and stars are properly aligned. I'm more inclined to think that, once again, the WDC data sheets are in error. Opinions?

There's a good chart at http://www.interfacebus.com/voltage_threshold.html

I don't think there's a conundrum, as such, it's just a question of what it means to "respond to CMOS input levels."

What that should mean is that a CMOS driver can successfully drive the input. As you say, CMOS drivers are specced to drive rather near the rails: let's say at or below 0.2x and at or above 0.8x for 0 and 1 respectively.

A CMOS driver would be out of spec if its output levels landed in the big dead zone between 0.2x and 0.8x.

But a CMOS-compatible input can be more generous: it doesn't have to built to malfunction if an input is in the dead zone. And so, not entirely coincidentally, it turns out that an input can be built to accept inputs from either a TTL driver or a CMOS driver - it has to be built to allow for a much lower voltage for logic 1.

The same reasoning applies to a CMOS output driver which can reliably drive a TTL input. It will need to source and sink sufficient current, and to drive logic low a little closer to the rail than is necessary to drive a CMOS input.

In both cases, the cross-compatible pin is in spec for its native technology, but not by thinnest margin, rather it goes beyond the spec for its native technology and can therefore operate reliably with the other technology.

Cheers
Ed

There is also this write-up, which I found to be useful in understanding the issues:

http://www.allaboutcircuits.com/textboo ... ge-levels/

It specifically states that TTL high levels can be outside of the scope of a CMOS high input. I've been pondering why my 6809 in NMOS, with most other parts in CMOS, board works so well, for the same reason. I can only think that the TTL spec is overly pessimistic, and perhaps relate to extreme temperature ranges or something.

It is instructive to have a look at the "totem pole" output stage of TTL logic:

https://en.wikipedia.org/wiki/File:7400_Circuit.svg

From examining the schematic, you can see that in a 5V circuit, V(OH) will never be more than about 3.5 volts, and considerably lower if the output is loaded. On CMOS logic, V(IL) is typically specified at 30% of VDD and V(IH) is typically specified at 70% of VDD. 70% of 5 volts is 3.5 volts, so an unloaded TTL high output just meets this threshold. In practice, however, most CMOS hardware will actually switch much closer to the 50% mark (good experiment to try, BTW) meaning you can often get away with driving CMOS logic with TTL logic at 5 volts.

If you want to build a more robust system incorporating both logic families, have a look at using (A)HCT parts to interface from TTL outputs to CMOS inputs.

Speaking of 6809s, isn't the 63C09 a CMOS variant, or is it merely an HMOS variant?

• Edit:
  jmp(FFFA) wrote:

  most CMOS hardware will actually switch much closer to the 50% mark (good experiment to try, BTW) meaning you can often get away with driving CMOS logic with TTL logic at 5 volts.
  Six years later, I *did* try this experiment! In 2021 I actually measured the switch point of the inputs on three 65xx microprocessors.
  
  As jmp(FFFA) pointed out, attaching TTL outputs to CMOS inputs may often work in practice. But it isn't a robust combination unless the CMOS inputs have a switch point (aka input transition point) well below 50%, as with the inputs of 74(A)HCT parts. Although the Rockwell 'C02 I tested did have a lowered switch point suitable for TTL levels, the experiment indicated that the WDC CPU's under discussion in this thread did not.
  
  WDC datasheets do certainly have a reputation for errors, but in this case I believe there is no mistake. The inputs of the WDC 'C02 and the WDC '816 I tested both switched at about 50%, corresponding to 74(A)HC parts, not 74(A)HCT. For details, see TTL Compatible... NOT! ( modern WDC CPU's ).
  ----------------------------------

It's maybe helpful to think about the simplest case, which is just Chip A driving Chip B. A's output will switch between logic-high and logic-low. The logic-high voltage and the logic-low voltage must satisfy the input of Chip B -- they must be "loud enough" for B to "hear." Unfortunately TTL outputs typically put out less than 3 volts when high. But TTL inputs are engineered to receive this -- TTL inputs have extra-good hearing. (Sorry about the corny analogy! )

CMOS driving TTL presents no voltage problem, because CMOS outputs switch virtually rail to rail, and TTL inputs respond to less than 3 volts.

TTL driving CMOS does present a voltage problem, because as noted TTL outputs may supply 3 volts or less when high, and ordinary CMOS inputs require about VDD × 0.8 -- ie; 4 volts when VDD is 5. (A pullup resistor will raise the voltage as required, but that's OT.) To recap, CMOS driving TTL presents no voltage problem. But TTL driving CMOS does present a voltage problem because ordinary CMOS inputs are somewhat deaf (as compared to TTL inputs).

Luckily it's possible for a manufacturer to alter the response of a MOS or CMOS input, and that accounts for the difference between logic chips from 74HC and 74AC families as compared to 74HCT and 74ACT families. Inputs for the latter are altered to accept TTL voltage levels.

The same altered input response is commonly featured on CPU chips, including the original NMOS 6502 -- and BTW all 65c02's except WDC. For example Rockwell 65c02's accept TTL compatible levels. WDC is an outlier in this regard. I suspect WDC omitted TTL-compatible inputs because of conflicting factors pertaining to battery operation (ie, Vdd below 5 Volts) but my guess could be wrong. In any case the need for TTL-compatible inputs has largely disappeared, thanks to 74LS being replaced by CMOS equivalents whose outputs switch virtually rail to rail.
Agree. Sorry, jmp(FFFA), I missed your post while I was typing my own. The 6309 (no "C") is a Hitachi super-6809, implemented in CMOS. It eliminates many of the 6809's all-too-numerous dead cycles and features a far more powerful programming model -- including extra registers and several 32-bit operations (!).

Despite what the datasheets may say, I experimented with a handful of HC logic chips I had on hand a few years ago and found that the threshold voltages were typically 50% +/- 10% in the small batch that I tried. Probably not a good idea to rely on this, but it does explain why some people have interfaced between the two logic families and not had problems. BTW, my TI 74HC00 datasheet has V(IH) specified at VDD x 0.7.
Are you suggesting a pullup resistor on the output of a non-OC TTL device? That might work for low-speed circuits, but I'm not sure it's a good idea for high-speed circuits as it would result in an uneven low-to-high transition that ramps to ~3.5V quickly and then slowly approaches VDD depending on the pullup resistance used and the capacitance of the load(s) driven.

There is also a 63C09 (HD63C09P is one example). I didn't recall whether it was an HMOS device (with the same interface issues as NMOS), or a CMOS device. I just looked it up and see that it is indeed a CMOS device, just like the 65C02. Pity they never made them faster than 3 MHz.

Yes. I agree with your concerns but if the pullup has a low enough value then they can usually be diminished to insignificance -- and replaced with a different set of problems. A low-value pullup wastes power and may tax the output-current capability of the chip that has to drive it. Thanks for the correction; I didn't know that.I agree with all my heart!!!

True -- and I confess I deliberately sidestepped the question of current. IMO the voltage questions are much more important to understand. But, FWIW:

In all cases (TTL/CMOS/whatever), the chip that's producing the output must charge and discharge whatever capacitance the circuit presents, including the inputs of other chips plus any stray capacitance. Charging and discharging capacitance requires a transient burst of current, and the transient lasts longer when the capacitance is excessive. In extreme cases this will limit speed but it's otherwise generally tolerable -- not a show-stopper.

In addition, it takes a small but significant current to pull a TTL input low (but not a MOS or CMOS input). This is a continuous, not transient, current requirement. When a large number of TTL inputs must be driven by a single TTL/MOS/CMOS output then a "fanout" limit will be encountered. IIRC a 74HC/HCT output can drive about ten LS-TTL inputs, so in practice it's a limit that most people will never encounter.

Gentlemen, this is all well and good, but doesn't explain why the SRAMs I mentioned in my original post appear to work flawlessly with the 65C02 and 65C816, despite having TTL-level outputs.

I suspect the RAMs have TTL-compatible output levels, not TTL output levels. What's the Voh?

Edit: wow, that is weird!! The CY7C1049D datasheets says, "Please note that the maximum VOH limit does not exceed minimum CMOS VIH of 3.5 V. If you are interfacing this SRAM with 5 V legacy processors that require a minimum VIH of 3.5 V, please refer to Application Note AN6081 for technical details and options you may consider."

With all these "fake" chips popping up out of China, they must have done something to reduce the cost of fabbing them to the point where they can make a profit on smallish runs of relatively cheap parts. In fact I've even heard of some universities here in the USA fabbing older (90-110 nm) dies in their VLSI graduate programs. Assuming one could get a circuit diagram or the lithography for a 63C09 out of Hitachi, I can't help but think it might be economical to make a run of a few hundred or thousand of them. I'm guessing a 90 nm 63C09 would have an F(max) quite a bit higher than 3 MHz. In fact, if this were feasible, imagine the fun we could have turning some of the modified 6502 designs implemented in HDL into real silicon parts in DIP or SMT format.

What I find weird is not the fact this Cypress RAM works with a CPU that doesn't accept TTL input levels. IMO that's sufficiently explained by the worst-case, conservative nature of Cypress's output spec's aided by the similarly conservative WDC input spec's.

What I find weird is the fact that there's a CMOS product that fails to generate CMOS output levels! I would've taken it for granted that that was inherent and invariable.

It looks like their recent (90nm) offerings are running a 3.3V I/O supply even though the chip supply is nominal 5V - would that explain everything?

It gets more interesting...the CY7C1049D's predecessor, the CY7C1049B, did produce CMOS output levels. The switch evidently came when Cypress moved the device to the 90nm process. It would be interesting to apply Vcc and ground to an SRAM, assert /OE and measure the actual voltage produced on the data pins. Even without applying anything to the address pins something should show up on D0-D7, as SRAMs power up into random states.

Incidentally, I read AN6081 and learned absolutely nothing from it that I didn't already know. Cypress doesn't really offer much useful advice in that app note.
It could be, although, again, the app note doesn't shed much light on it.