6502.org

Was wondering if there was any particular reason why the CMP, as well as the INC, DEC etc. instructions don't affect the overflow flag on the 6502. I'm designing my own processor (a simplified, fixed-length instruction, derivative of the 6502) and wanted to make sure I'm not missing anything with implementing the overflow flag one way over the other.

Just my two cents. I think that it was an error. The SBC instruction sets the V flag for binary arithmetic. CMP only modifies the PSW unlike the SBC instruction which modifies both the PSW and the accumulator, A. This leads me to believe that it was an oversight that was never corrected. As many on the site have said, performing signed comparison with CMP is difficult and requires more code than would be needed if the instruction also set the oVerflow flag. I can't conceive of another reason for not implementing ADC, SBC, and CMP to modify all four arithmetic flags.

That's how I felt about it as well. Signed comparisons as well as other functions become more complicated in absence of it. I'm having a wonderful time trying to discover all the little quirks of the 6502 that can be improved upon in a revision of the processor. Thanks for the insight!

If you talk about the missing overflow flag on compare you should also note, that there is no compare with carry (-borrow) input. So comparing larger than 8-bit numbers (for < or > only) requires the use of SBC anyway.

Having the V-flag on INC and DEC is state of the art in current processors but it isn't as usefull as having a CPC instruction setting the overflow flag. INC or DEC without comparing to a fixed number or Z-flag ahead of a potential overflow is very rare.

Welcome, lookaside! Did you think you would use discrete ICs for your new processor, or an FPGA of some kind? I hope you'll keep us posted on your plans & progress.

-- Jeff

Indeed, welcome, lookaside... I checked the PDP-11 and it sets and clears overflow in many more situations, (as does the 6800) so the 6502 hasn't inherited this decision from there. I checked the circuitry for setting the V bit from the ALU, and I see that a single line of the PLA is enough to decode the 16 ADC and SBC operations, and this line feeds into a single logic gate to bring the V output of the ALU into the V bit. So, to have other operations also affect the V bit would mean having at least one more and possibly several more lines of the PLA, and making that logic gate correspondingly more complex. Perhaps, then, it wasn't done because there was a cost, and also because there wasn't a need - V from arithmetic is very useful, evidently V from comparison or increment/decrement less so.

Here's the wire which does the work:
http://visual6502.org/JSSim/expert.html ... 1&zoom=2.4

Thank you all so much for the information! The mention of having a CPC instruction is very interesting and I'm sure I could fit it in my instruction set. Very cool that you can link to individual wires on the 6502 in that diagram! That was also interesting to look at.
A little bit about what I'm attempting to do here, I'm only 16 and don't have as much knowledge in electronics as I would eventually like to. I've been teaching myself all I could on computer architecture the last 3 years and built several simple processors in simulators. This project is heavily inspired by the 6502 (which I increasingly love as I learn more about it). It is a 7 stage (so far) pipeline with 16 bit fixed-length, single-cycle instructions. The instruction set falls short of the 6502 in its lack of one of the index register, and the number of addressing modes for each instruction.
I'm currently building it in Logisim (my favorite sim out of the dozens I've tried), and afterwards might try to build it in the game Minecraft. I'm also trying to build a SUBLEQ computer out of ICs to learn more about electronics, and hopefully I could do the same for this processor.
I'm very much enjoying browsing this forum so far, and I'd love to post some documentation for this project soon to receive feedback and criticism. Looking forward to growing and learning more through this community. Thanks for the warm welcome!

Excellent ideas there! And you have lots of time to catch up with those of us who are even older than the 6502 itself.

As a slightly random link, I saw the other day an online EDA gateway where you can use industry standard tools to do your designs online: see
http://eda-playground.readthedocs.org/e ... intro.html
http://www.edaplayground.com/home
(Another approach is to download the free tools from FPGA vendors - you can then design, simulate, debug as much as you like, whether or not you eventually implement in FPGA.)

But, starting with whatever you have is a fine idea. Building a CPU in Minecraft is amusing and interesting, for sure - as far as I can tell no-one has actually tackled a 6502 yet. As with all 6502 re-enactments, the bidirectional gates in the original microarchitecture would probably be a challenge.

(You might already be past this point, but the nand2tetris project gets good reviews.)

Cheers
Ed

6502 has been done in Minecraft, I'm sure it was talked about on this forum also. But it's been a few years. http://hackaday.com/2012/05/20/building ... minecraft/
But there's definetely room for one more!

-Tor

lookaside, it sounds like you're doing great! For ideas, be sure to look at the CMOS 65c02 also, and the 65816. The 65c02 has more instructions and addressing modes than the original NMOS 6502, and fixes all the NMOS bugs, and the '816 adds the option to run the registers in 16-bit mode and adds lots more instructions and addressing modes, making it able to do things that the 6502 was either clumsy at or totally unable to do. It has a 16MB address space, movable ZP, 64K stack space, and a lot of other attractions. For ideas from other 6502 versions that have been made or at least designed, see the "65-family processors" section of my links page, at http://wilsonminesco.com/links.html#65fam .

Sadly, not really - there's a CPU module thing which you can add into your Minecraft, which looks a little like a 6502, but it's not a CPU implemented in Minecraft's own physics, like this for example.

PFFT that doesn't count! That was a software emulator of the 6502 implemented with mods. Literally does not use any of Minecraft's physics. My project would be vanilla Redstone. Also my project isn't a complete replica of the 6502, rather an architecture that takes heavy inspiration from it. The 6502 would perform terribly in Minecraft compared to the pipelined architecture I have planned.