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Starting with ATMEL CPLDs: ATF1504AS
Posted: Sat Apr 18, 2015 1:52 pm
by cbscpe
Hi,
after many suggestions by BDD I finally took the step and decided to go with those fancy ATMEL CPLDs available for 5V and as expected I start having some questions. But first let's talk about my environment. So far I have some of these PL-44
http://www.futurlec.com/PLCC_Adapters.shtml the ATMEL USB progamming cable from here
http://www.kanda.com/CPLD-Programmers.175.html. As always deliveries from UK to CH are a pain ... they are expensive and take a long time, not only because of parcel service but mostly because of swiss customs, but I wanted to get a genuine one and not a fake from china. At the end it cost me the double as listed on the vendors page. But that's not his problem, thats mainly because Switzerland is not EU
. And last but not least a few ATF1504AS10JC44 to play with. I have installed ATMEL ISP and it recognizes the cable.
- ATMEL ISP successfully detects programming cable
Then I have installed WinCUPL. Now I have a question. What is the recommended Syntax for a 17-input multiplexor. I want to create a multiplexor with about 20 input signals that selects one of the inputs (and also the status of outputs created by the CPLD itself) depending on the address the CPU reads. The addresses for this application are scattered anywhere in the IO Page so that's why the almost random addresses. I thought this should work
Code: Select all
Name AppleIIe-IO ;
PartNo 00 ;
Date 18.04.2015 ;
Revision 01 ;
Designer Engineer ;
Company company ;
Assembly None ;
Location ;
Device f1504plcc44 ;
/* *************** INPUT PINS *********************/
PIN 1 = !RES ; /* */
PIN 2 = A0 ; /* */
PIN 3 = A1 ; /* */
PIN 5 = A2 ; /* */
PIN 6 = A3 ; /* */
PIN 7 = A4 ; /* */
PIN 8 = A5 ; /* */
PIN 10 = A6 ; /* */
PIN 11 = A7 ; /* */
PIN 12 = OA ; /* */
PIN 13 = CA ; /* */
PIN 14 = RW ; /* */
PIN 15 = !IO ; /* */
PIN 18 = PHI2 ; /* */
PIN 19 = KEY ; /* */
/* *************** OUTPUT PINS *********************/
PIN 20 = TEXT ; /* */
PIN 21 = MIXED ; /* */
PIN 22 = PAGE2 ; /* */
PIN 23 = HIRES ; /* */
PIN 25 = RAMRD ; /* */
PIN 26 = RAMWR ; /* */
PIN 27 = CXROM ; /* */
PIN 28 = C3ROM ; /* */
PIN 30 = ALTZP ; /* */
PIN 31 = STO80 ; /* */
PIN 32 = COL80 ; /* */
PIN 33 = ALTCH ; /* */
PIN 34 = ROMRD ; /* */
PIN 38 = RDLCR ; /* */
PIN 42 = BANK2 ; /* */
PIN 43 = DOUT ; /* */
PIN 44 = !KBD ; /* */
/* *************** PINNODES *********************/
PINNODE = STRB ; /* */
PINNODE = ANN ; /* */
PINNODE = INP ; /* */
PINNODE = INPA ; /* */
PINNODE = RAMPR ; /* */
PINNODE = K7 ; /* */
PINNODE = TEMP2 ; /* */
PINNODE = TEMP3 ; /* */
/* Declarations */
K7 = K7 & !RES & A7 /* Keep when A7 = High */
# K7 & !RES & A6 /* or A6 = High */
# K7 & !RES & A5 /* or A5 = High */
# K7 & !RES & !A4 /* or A4 = Low */
# K7 & !RES & A3 /* or A3 = High */
# K7 & !RES & A2 /* or A2 = High */
# K7 & !RES & A1 /* or A1 = High */
# K7 & !RES & A0 /* or A0 = High */
# K7 & !RES & !PHI2 /* or PHI2 = not asserted */
# K7 & !RES & !IO /* or IO = not asserted */
/* clear on $C010 with PHI2 = high */
# KEY ; /* set when key is waiting */
FIELD ADDRESS = [A7..0];
FIELD RDSSW = [DOUT];
Table ADDRESS=>RDSSW {
[00..0F] => K7;
[11] => BANK2;
[12] => !ROMRD;
[13] => RAMRD;
[14] => RAMWR;
[15] => CXROM;
[16] => ALTZP;
[17] => C3ROM;
[18] => STO80;
[1A] => TEXT;
[1B] => MIXED;
[1C] => PAGE2;
[1D] => HIRES;
[1E] => ALTCH;
[1F] => COL80;
[61] => OA;
[62] => CA;
}
It says
Code: Select all
77: [00..0F] => K7;
[0002ca] invalid number: K7
I must say I'm a bit lost. Of course I could use standard equations, but I wanted to use a Table as this is much easier to read and understand especially as here the address read is the important key for the input to select. Any hints what I did wrong?
cheers
Peter
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sat Apr 18, 2015 7:12 pm
by BigDumbDinosaur
It says
Code: Select all
77: [00..0F] => K7;
[0002ca] invalid number: K7
I must say I'm a bit lost. Of course I could use standard equations, but I wanted to use a Table as this is much easier to read and understand especially as here the address read is the important key for the input to select. Any hints what I did wrong?
At first glance, you have
K7 on both sides of an equate statement, which I believe is not permissible syntax, viz:
You are in effect making pinnode
K7's state contingent on its state. Try removing all right-side references to
K7 in that statement and recompiling.
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sat Apr 18, 2015 7:43 pm
by cbscpe
Hi BDD,
to have K7 on both sides is completely legal. There are even examples. It's just a special way of doing R-S-Latches. What I found is that the following change (note the 1& in front of each signal)
Code: Select all
FIELD ADDRESS = [A7..0];
FIELD RDSSW = [DOUT];
Table ADDRESS=>RDSSW {
[00..0F] => 1 & K7;
[11] => 1 & BANK2;
[12] => 1 & !ROMRD;
[13] => 1 & RAMRD;
[14] => 1 & RAMWR;
[15] => 1 & CXROM;
[16] => 1 & ALTZP;
[17] => 1 & C3ROM;
[18] => 1 & STO80;
[1A] => 1 & TEXT;
[1B] => 1 & MIXED;
[1C] => 1 & PAGE2;
[1D] => 1 & HIRES;
[1E] => 1 & ALTCH;
[1F] => 1 & COL80;
[61] => 1 & OA;
[62] => 1 & CA;
}
solves the issue, but I don't know why. When I look at the at the .fit file it really does the following
Code: Select all
DOUT = ((A4 & !A5 & !A6 & !A7 & !A0 & A1 & A2 & A3 & ALTCH)
# (A4 & !A5 & !A6 & !A7 & !A0 & A1 & A2 & !A3 & ALTZP)
# (A4 & !A5 & !A6 & !A7 & A0 & !A1 & !A2 & !A3 & BANK2)
# (A4 & !A5 & !A6 & !A7 & A0 & A1 & A2 & !A3 & C3ROM)
# (!A4 & A5 & A6 & !A7 & !A0 & A1 & !A2 & !A3 & CA)
# (A4 & !A5 & !A6 & !A7 & A0 & A1 & A2 & A3 & COL80)
# (A4 & !A5 & !A6 & !A7 & A0 & !A1 & A2 & !A3 & CXROM)
# (A4 & !A5 & !A6 & !A7 & A0 & !A1 & A2 & A3 & HIRES)
# (A4 & !A5 & !A6 & !A7 & A0 & A1 & !A2 & A3 & MIXED)
# (!A4 & A5 & A6 & !A7 & A0 & !A1 & !A2 & !A3 & OA)
# (A4 & !A5 & !A6 & !A7 & !A0 & !A1 & A2 & A3 & PAGE2)
# (A4 & !A5 & !A6 & !A7 & A0 & A1 & !A2 & !A3 & RAMRD)
# (A4 & !A5 & !A6 & !A7 & !A0 & !A1 & A2 & !A3 & RAMWR)
# (A4 & !A5 & !A6 & !A7 & !A0 & A1 & !A2 & !A3 & !ROMRD)
# (A4 & !A5 & !A6 & !A7 & !A0 & !A1 & !A2 & A3 & STO80)
# (A4 & !A5 & !A6 & !A7 & !A0 & A1 & !A2 & A3 & TEXT)
# (!A4 & !A5 & !A6 & !A7 & !K7));
K7 = ((!KEY & K7)
# (!KEY & !A0 & !A1 & !A2 & !A3 & A4 & !A5 & !A6 & !A7 & !IO & PHI2)
# (!KEY & !RES));
Especially the code for DOUT is exactly what I expected. As for the code for K7, it's the inverse logic of K7 and as one can see in the last term of DOUT he did that on purpose to save terms. Good idea from CUPL I never tried that trick.
However as it seems, WinCUPL is not really bug-free. In the .fit file he shows me the following layout
Code: Select all
D
O V G
A A U C N
1 2 T C D
____________________________________
/ 6 5 4 3 2 1 44 43 42 41 40 \
A0 | 7 39 |
A7 | 8 38 | RES
A6 | 9 37 | PHI2
GND | 10 36 | IO
A5 | 11 35 | VCC
A4 | 12 ATF1504 34 | KEY
CXROM | 13 44-Lead PLCC 33 | TEXT
COL80 | 14 32 | STO80
VCC | 15 31 | ROMRD
CA | 16 30 | GND
C3ROM | 17 29 | RAMWR
| 18 19 20 21 22 23 24 25 26 27 28 |
\____________________________________/
B A A A G V H M O P R
A L L 3 N C I I A A A
N T T D C R X G M
K Z C E E E R
2 P H S D 2 D
which is not true. Because in the .pin file he tells me the following
Code: Select all
A4 : 12
A5 : 11
A6 : 9
A7 : 8
A0 : 7
A1 : 6
A2 : 5
DOUT : 4
PAGE2 : 21
MIXED : 20
HIRES : 19
CXROM : 18
COL80 : 17
C3ROM : 16
ALTZP : 14
K7 : 631
ALTCH : 13
A3 : 24
IO : 25
PHI2 : 26
STO80 : 28
TEXT : 29
RAMWR : 31
RAMRD : 32
CA : 33
OA : 34
ROMRD : 36
KEY : 37
BANK2 : 39
RES : 1
which is wrong as well. First I used the layout in the .fit file because I thought this is nice. As you can imagine my SBC did not like that his A3 was in fact connected to PAGE2 which is a permanent output. The .pin file is also wrong PIN 24 is ties A3 to low as well, so the question is where has my A3 input gone
Probably I have to fix the PIN numbers by hand. What do you normally do? Do you let the fitter decide which pin goes to which number or do you do it by hand? And in either case what is your experience?
Cheers
Peter
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sun Apr 19, 2015 6:18 am
by BigDumbDinosaur
to have K7 on both sides is completely legal. There are even examples. It's just a special way of doing R-S-Latches. What I found is that the following change (note the 1& in front of each signal)
Code: Select all
FIELD ADDRESS = [A7..0];
FIELD RDSSW = [DOUT];
Table ADDRESS=>RDSSW...
solves the issue, but I don't know why.
There are problems with the FIELD functions, which led me to abandon them, since I often ended up with code that either would not simulate or didn't produce the expected logic.
However as it seems, WinCUPL is not really bug-free. In the .fit file he shows me the following layout...Probably I have to fix the PIN numbers by hand. What do you normally do? Do you let the fitter decide which pin goes to which number or do you do it by hand? And in either case what is your experience?
I always assign pins. The fitter does make mistakes now and then. You just have to be careful to not make too many connections on one side of the device, as you will run out of resources.
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sun Apr 19, 2015 8:17 am
by cbscpe
Hi BDD,
so far I have some success (or I should say I made a big step forward). The reasons for my problems (except one that I have to address now) were the following.
Fields are numbered from right to left as already pointed out by 8Bit. So the following do really select the correct address or address ranges.
Code: Select all
FIELD ADDRESS = [A7..0];
Table ADDRESS=>DOUT {
[00..0F] => 1 & K7;
[11] => 1 & BANK2;
[12] => 1 & !ROMRD;
Also you need to have as many "fixed" bits (a constant of appropriate length) on the output side as you have in the table statement. Because you create the same number of outputs in all statements. In my case I have one output (DOUT) so I must always select it. If you want to make a n-to-1 multiplexor you need then to add the signals after the bit fields. In the other thread with the input from 8Bit banedon did show that very nicely (
viewtopic.php?f=10&t=3257&start=15#p37410). This makes address decoders very easy to read in fact. I think fields and tables do work.
Then one huge problem with WinCUPL, once you have opened one of the result files (e.g. .fit or .io) he does not update the screen when you re-compile the design so what you see on the screen is the previous result. You need to close the window and then select the file again, that explains the problems that I was thinking the fitter did something wrong. So now before compiling a design I close all files or even re-open the project to make sure I have a fresh start on the display.
So now I have my design with the pins allocated by the fitter as follows
Code: Select all
B
D A
O V R K G N
A A U C A E E N K O
3 0 T C 6 S Y D 2 A
____________________________________
/ 6 5 4 3 2 1 44 43 42 41 40 \
TDI | 7 39 | CA
A7 | 8 38 | TDO
RW | 9 37 | PHI2
GND | 10 36 | IO
A5 | 11 35 | VCC
A4 | 12 ATF1504 34 | A2
TMS | 13 44-Lead PLCC 33 | A1
WRRAM | 14 32 | TCK
VCC | 15 31 | ROMRD
ALTZP | 16 30 | GND
ALTCH | 17 29 | MIXED
| 18 19 20 21 22 23 24 25 26 27 28 |
\____________________________________/
C C C H G V S T R P R
3 X O I N C T E A A A
R R L R D C O X M G M
O O 8 E 8 T W E R
M M 0 S 0 R 2 D
And I now I find my A3 and the other signals
. I successfully programed and verified the chip and now I'm debugging my design. So far I found that the way I generate clock for internal flip-flops is somewhat not correct, I wanted to qualify it with PHI2 but it seems I screwed up the equation (I don't show it now, because I'm sure the mistake I have here is so basic that I would be ashamed to ask, I need to fix that myself). As you see the design uses all but one pin with the JTAG pins unused. So I can always go back using ISP.
So far what I can say, everything is straight forward and I spent much less time than anticipated to get this far. Now I just have to order the TQFP-44 versions and solder them on my DIP-48 adapters to make efficient use of bread-board space.
I have one question, once you use the TDI, TDO, TCK and TMS pins for your design you can't program the chip using ISP anymore? Is that correct? What do you do then? Is there a way to at least clear/reset the chips without a professional (aka rather expensive) programmer?
cheers
Peter
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sun Apr 19, 2015 8:46 am
by BigEd
Good work Peter - great to have explanations and guidance for how to get software to work right.
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sun Apr 19, 2015 4:34 pm
by BigDumbDinosaur
I have one question, once you use the TDI, TDO, TCK and TMS pins for your design you can't program the chip using ISP anymore? Is that correct? What do you do then? Is there a way to at least clear/reset the chips without a professional (aka rather expensive) programmer?
That is correct. ISP is not possible if any of those pins are used in your design. You need some kind of a programming rig to program the device while it is out of the circuit.
However, you could attach the JTAG pins to a jumper block so you could isolate them from the rest of the circuit and then rig up a JTAG port. I haven't investigated doing such a thing, however.
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sun Apr 19, 2015 4:48 pm
by BigEd
You'd be OK using TDO as an output, surely? You can still tap it for TAP.
Using the inputs is more tricky as you don't want to contend against whatever's driving them - but if the driver can be tristated, or is an off-board connector, or comes from a socketed part, or you put in a jumper, then you should be OK.
Isn't that so?
Edit: oops, no, that isn't so. At minimum, TMS would need to be dedicated - how else could the chip know whether it was being used or being programmed. But it may be that the chip is designed as all-or-nothing - if you use any of the 4 JTAG pins, the JTAG engine will be disabled.
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sun Apr 19, 2015 7:29 pm
by cbscpe
As far as I can see, once you program the device with a design that makes use of the JTAG interface the JTAG interface is locked and no longer available. In the datasheet it says
The ATF1504AS has an option of using four JTAG-standard I/O pins for boundary-scan testing (BST) and in-system programming (ISP) purposes. The ATF1504AS is programmable through the four JTAG pins using IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins.
for me it is either JTAG or four additional IO pins. There are as well other sections that refer to 3rd party programmers that must be used if you want to use those additional IO pins. The datasheet also mentions a programming voltage of max +14V. So there is a high-voltage procedure to program the chips.
Anyhow, I found the reason for the issue with some equations I mentioned in a previous post of this thread and now I could successfully test at least some (due to lack of time only) of the functionality in real hardware. Fortunately my design by coincidence requires exactly 32 pins, the maximum with ISP programming as it seems.
So indeed the only thing to successfully design and program these 5V CPLDs is a ATMEL ISP USB cable, ATMISP software (which comes with the cable) to download the JEDEC file and a design software that supports the ATF15xx, like WinCupl from ATMEL.
cheers
Peter
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Sun Apr 19, 2015 8:28 pm
by BigEd
Oh, well that would be a shame. I would think using TMS is the only thing which should preclude mixed-use.
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Fri May 01, 2015 8:19 am
by cbscpe
Hi,
I have some questions and "google" was no help at all. It seems that information about how to design a ATF1504/8 CPLDs in WinCUPL is rather scarce. Anybody knows of some more elaborate documentation or books? I really would appreciate more information. So back to my question.
I want to create an addressable latch that can be set and reset by addressing two memory locations. At the same time I want to be able to use the state of this latch internally but I also want to be able to read the status of the latch externally via a tri-state output. So far only this design is successfull
Code: Select all
/* *************** INPUT PINS *********************/
PIN 1 = !RES ; /* */
/* *************** OUTPUT PINS *********************/
PIN 25 = TEXTO ; /* */
/* *************** PINNODES *********************/
PINNODE = TEXT;
TEXT.CE = (IO & !A7 & A6 & !A5 & A4 & !A3 & !A2 & !A1);
TEXT.CK = !PHI;
TEXT.D = A0;
TEXT.AR = RES;
/* TEXT.OE = 'b'1; */
/* I did not find how
TEXTO = TEXT & !RES;
TEXTO.OE= OA;
Only then I can use TEXT internally to be the status of the latch. However this design uses 2 macro-cells a burried one (TEXT) and another one connected to an IO Pin (TEXTO). The combinatorial logic of TEXTO with RES is required else WinCUPL will eliminate (optimiziation) it. After optimization TEXT does not reference the output of the latch but the state of the PIN TEXT, and when it is tri-stated this is whatever is feed on the PIN. Needless to say this does not work, as this pin normally is connected to the data-bus of the 6502. Any Idea how I can eliminate the second macro-cell. Normally you would force CUPL to use the output of the register by using some extension, but .dfb is not recognized as valid extension for the ATF1504.
As for the ISP JTAG interface I can confirm, it really is an either/or decision you have to make. Either the 4 pins are all dedicated to the JTAG interface for ISP or, when you only use one of these pins, JTAG is disabled altogether and only HVP can access the chip after you program the chip. And a HVP programmer is exactly what I want to avoid, as these devices cost a lot (and with a lot that means more then 500USD for programmers that support the ATF1504 and have USB!).
Cheers
Peter
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Fri May 01, 2015 8:26 am
by BigEd
(Thanks for confirming the JTAG situation)
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Fri May 01, 2015 9:57 am
by GARTHWILSON
I have some questions and "google" was no help at all. It seems that information about how to design a ATF1504/8 CPLDs in WinCUPL is rather scarce.
What search terms did you use? Google is not the only search engine, or even necessarily the best. I use ixquick.com (which does not have the political and privacy issues that Google does), and typed in "ATF1504/8 CPLDs WinCUPL", and the top results looked good.
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Fri May 01, 2015 1:01 pm
by cbscpe
Hi Garth,
the first I get with your search terms is the download page for WinCUPL from ATMEL. I searched a lot in various search machines and any combination of cpld, atf150xx and wincupl shows more or less the same information.
- Macro Cell
Perhaps a picture of what I want shows what I want to achieve. I have a registered cell and I want to feedback the output Q (red arrow) to be used internally but still I want to be able to read the state of the register via the tri-state buffer (green arrow), which of course requires that the MUX between the tri-state buffer selects the path from Q.
Generally speaking, I'm looking for a manual that explains which extension must be used to select a given path or set a specific MUX. According to the help this is the default. But it's not working. And the extension to force the default (.dfb) generates a warning.
Peter
Re: Starting with ATMEL CPLDs: ATF1504AS
Posted: Tue May 12, 2015 11:40 am
by cbscpe
Hi,
to save real-estate on my breadboards and to have my favorite IC form factor (DIP) I have create a few of these for my projects that use a ATF1504AS CPLD.
after various tests and small projects (some sort of "Hallo World" and "Blinkenligths" for CPLDs) I will now start with a new SBC using one of the DIP-48 format CPLDs. Surprisingly these are quite powerfull and a full decoder with memory mapping and ROM overlay logic can be easily put into one single ATF1504AS.
cheers
Peter