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Hello, on my first 6502 project i have to divide the address space between 3 RAM chips, 3 ROM chips and a VIA. I know how this works, but i was just wondering if there is any tool available or formula of some kind to help me do this the most efficient way possible? I plan on using some 3 to 8 memory decoders.

Have you checked Garth's very nice page on address decoding, to see if he has something suitable for your proposed configuration?

http://wilsonminesco.com/6502primer/addr_decoding.html

Mike B.

Perhaps if you could post your proposed memory map we may be able to offer some suggestions.

Welcome, yvibod! With a single 3 to 8 decoder you can split the 64k address space into 8 sections of 8k each. You have 7 devices to fit in, so if all the devices are 8k or smaller, you're already finished!

As BDD notes, more information is needed to solve the problem. But to answer your question, I don't know of any tool or formula: understanding what's happening and knowing what you want to do leads relatively directly to a solution: you are splitting or merging blocks of memory which have a power-of-two size. An efficient design will not decode any more finely than necessary: having a single VIA mapped over an entire 16k is a viable solution for some cases. For other cases, you'd want to map the VIA all the way down to a 16-address window. And there are many intermediate cases.

I second Mike's recommendation to read Garth's primer.

Cheers
Ed

Thank you for the suggestions, the chips are 3 RAMs of 3K each at the beginning of address space, 3 ROMs of 3K each at the end and a VIA at the beginning of the second 32K bank. Before I made the question I was looking for at tool that would do this sort of work but now I tried doing it by hand it isn't that hard really.

Each memory chip is 2K, if i put them in 8k blocks there would be a gap between them right? Would that be a problem?
I was trying to organize it in a way that all the ram would form a single 6k block.

In that case, you may want to use an 7-way decoder to split the memory into 8k blocks, and a 4-way decoder to split a particular 8k block into 4 2k blocks. This may not be ideal in terms of propagation delays, but it used to be fairly common.

The 74LS138 is an example of an 8-way decoder, while the 74LS139 has two 4-way decoders in a single package. Note: depending on what technology your other components use, you will probably want to use a different chip family than 74LS.

I dont think propagation will be much of a problem, since i'm only working at 1Mhz. Thanks for the recommendation on the decoders, I don't have those chips but they should be easy enough to get.

3k RAM seems a really unusual size to me - what part are you using?

You'll want the RAM contiguous so programs don't don't have to jump over dead or mirrored spaces, and so you can have contiguous data arrays. Why not just spend a few dollars on a 32Kx8 SRAM? It will pay for itself in the reduced number of sockets required, the labor to wire-wrap it all, and in board space.

I'd love to, but i live in South America and it's a real pain to buy some components, so i'll have to use what i have.

Sorry, it's actually 2K. It's a HM6116P for RAM and a XLS28C16BP for ROM

Ah, that's more like it! So, indeed, having decoded down to 8k blocks, you need to decode two more address bits to get to a 2k size. There is such a thing as a 2-to-4 decoder, or you could use some NAND or NOR gates probably.
Edit: or indeed use another 3 to 8 decoder, if that's what you have, and tie off an input.

Just got back from the store with some 74LS139! They are cheap so i got some on my way home. So I'll connect the 3-8's inputs to the top three address lines, A15 A14 and A13 to divide the address space into 8K blocks, when I reach the block I need, say the first for the RAM, the equivalent 3-8 output will hit the enable line of the 2-4. The 2-4 will be connected to A14 and A13? since 8k in binary is 10000000000000?
Not sure about that last part.

You need to decode A12 and A11 to decide which 2k block is active.