6502.org

In this new project I am trying to build a modular system out of 5x10 cm boards.
The reason the boards are so tiny is that large pcb-s are expensive, so I am trying to keep it tight.
I made a schematic for the CPU module, with bus amps, and what worries me is that the buffering might generate some signal timing issues.

Timing issues of what nature? I see you are using the 74ABT245 transceiver, which has a worst-case input to output propagation time of of 4.6ns over the full temperature range. That's vanishingly small compared to the shortest cycle time that an NMOS 6502 can manage. Something that would be of much greater concern would be ringing caused by the extremely rapid rise and fall rates of the '245 outputs.

Off topic a bit, but your schematic shows the 6502's SO input tied to ground. SO should be tied to Vcc. No resistor is required, unless you have plans to use that signal in some way.

Yes, that might be an issue. I'll try putting terminators on the other end of the bus to prevent that. Just not sure yet what would fit better, resistors or schottky diodes.
Oops, my mistake, thanks!

Schottky arrays are available that simplify bus termination. You may be doing some experimentation to find out what works best.

Dr. Howard Johnson, the high-speed digital-design industry guru, has a column on diode terminations at https://web.archive.org/web/20080705140 ... s/2_19.htm . He says they have their place (particularly on slower signals where the diode will actually be fast enough to help), but are not useful for solving certain reflection problems. What do you expect to put on the buses that will need the bus drivers? I made my first 6502 computer (1985, 2MHz IIRC) without them and it worked with a lot of loads on the buses even though its NMOS output drivers were not as strong as the currently made CMOS ones.

His schematic indicates that the buses will be going off-board.

Is it a mistake? My understanding is that /SO, like /NMI, is an edge-triggerred input activated by a negative-going transition. So, I'd say if you're not using /SO you have the freedom to tie it high or low simply according to convenience. Same with /NMI. The goal is to prevent a transition. But I'm willing to be corrected on this point if a reference can be cited.

-- Jeff

Interesting spot Jeff! Visual6502 appears to confirm what you say - in fact by default it runs all the time with the SO pin (strictly, the /SO pin) tied low. On bringing the pin high, nothing happens, as you'd expect, and on bringing it low again there's a one-cycle pulse on the control line 1069 which goes off to set the V flag. Nothing more happens for as long as it's held low.

Can anyone recommend a schottky diode model that is easily obtainable and affordable in large quantities?
I prefer trough hole for now.

Edit: I need the drives for tristating the bus too, so I can have another device access the bus.

Two things:

1- I think the clock select jumper is incorrect as one end goes to ground, shouldn't it go to "Eclk" on the 36-pin connector?
2- The W65C02 can put it's address and data buses in high impedance mode via the BE signal negating the need for the 245 drivers. However, you might need to change the use of the PH1 clock signal as it may not function properly with the WDC part.

Any particular reason you are choosing an older NMOS part?

Ah, the jumper, actually that is what I wanted.
I wanted to have a spot where I can connect an external source, so the ground is just for the external cable to have a proper ground connection.
As for using old NMOS, I got quite a few of those, but I also have a R65C02. Being a retro project itself, why just not use the original version of the cpu and see how much can I get out of it. Besides, it is just a CPU module, I'll be making more of those in the future.

I already made a second version of that board with a binary counter as clock divider, so I will be able to test various 6502 chips and see how fast each of those can go.

Yes, SO is edge triggered, so tying it to ground is technically not a mistake. My policy with unused signals that cannot be allowed to float is to tie them to the voltage level that is equivalent to quiescence. Ergo I'd tie SO (SOB in the 65C02) to Vcc, but through a resistor in case I suddenly decided that I need it for something.

Incidentally, the 65C02 timing diagram indicates that SOB is sampled on the rise of Ø2, unlike other 65C02 control inputs. I wish the 65C816 had SOB, as it would have been useful in my SCSI setup.

Please see attached for a suggestion.

Well spotted - and indeed, visual6502 shows that the signal is first inverted and then taken through a phi1 pass gate. That will have the effect of sampling on the falling edge of the chip's phi1, which should be referenced to the rising edge of phi2, as you say. (It has that effect because phi2 is later in play as well, which removes the transparency of the first latch.)

Nice, but looking on ebay they tend to be a bit expensive.