Donald F. Hanson's 6502 Diagram

[Bryan Parkoff]

Hi,

I asked about Control Flip-Flops in Random Control Logic last year. Six latches are POS, NOCR, SD1, SD2, CS, and I/V. Nobody knew the answer. After I completed analyzing Visual 6502, I believe I finally know the answer.

I/V is set overflow to Processor Status Register's Overflow flag. The letter 'I' is possibly stands for 'Insert' unlike 'Interrupt'.

SD1 and SD2 are for Read-Modify-Write. 'S' stands for Source. 'D' stands for 'Destination'. Read-Modify-Write gives one Read only and two Writes only on R/W pad. SD1 is enabled during first write as 'Modify'. SD2 is enabled during second write as 'Write'.

NOCR stands for no carry. It is for no page boundary crossing. If NOCR detects the page boundary crossing, then it tells the Timing Generation Logic to delay one more clock cycle before reaching T0.

POS is for branch to handle page boundary crossing. It is like position.

CS stands for carry shift. It is for rotate 9 bits including carry in the right position.

I have no idea why the diagram mentions three extra latches in Timing Generation Logic as T1, T1X, and T6. T0 and T1 share T0's latch as inverted T0 becomes to T1. I don't know what T1X means, but it refers T+ as mentioned in Visual 6502. T+ or T1X is supposed to be inverted T1. The non-inverted T1 goes to T2's latch, SYNC, and some parts of Random Control Logic.

The Timing Generation Logic should have five latches instead of eight latches. I will go further to do more investigation when I continue to analyze more later.

Take care,
Bryan Parkoff

[BigEd]

Thanks for figuring that out and letting us know.