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11.1. New Clock 
---------------------------------------------------------------------------

The new clock implements a state machine which allows to
dynamically switch between a Full and Half-frequency PHI2 cycle


The state machine has 2 bits, PHI2 and PHI3 which implement a
state machine with 4 states, it will use the already existing
74AC74.

The statemachine requires a input to select between the 
fast and the slow cycle. There are 2 versions of the state
machine depending whether the signal is Low or High for 
fast cycles

Version A: /SLOW is asserted (LOW) for slow cycles


            74F153         74F74


            +-----+         +-----+
   /SLOW----|I0   |  +------|     |--+--- PHI2
       VCC--|I1  Y|--+      | ST2 |  |
       VCC--|I2   |       +-|>    |  |
       GND--|I3  E|o-+    | |     |  |
            |A   B|  |    | |     |o----- /PHI2
            +-----+  =    | +-----+  |
             |   |        |          |
             +---|-------------------+
             |   |        |
             |   +-------------------+
             |   |        |          |
            +-----+       | +-----+  |
       VCC--|I0   |  +------|     |--+
       VCC--|I1  Y|--+    | | ST3 |
       GND--|I2   |       +-|>    |
       GND--|I3  E|o-+    | |     |
            |     |  |    | |     |o--
            +-----+  =    | +-----+
                          |
          ----------------+



ST2	0	1	0	0	1	1	0
ST3	0	1	0	1	0	1	0
State	0 --->	3 --->	0 --->	2 --->	1 --->	3 --->	0

The change from 0 depends on the input signal


		ST3	ST2
0 --->	3	1	1	Fast
0 --->	2	1	0	Slow

The following state changes are fixed

		ST3	ST2
1 --->	3	1	1
2 --->	1	0	1
3 --->	0	0	0

As we can see ST3 always toggles so we can also use /ST3
as input to D3, D2 has a more complex logic

D2	= /ST3	* /ST2	* /SLOW
	+ /ST3	*  ST2
	+  ST3	* /ST2


Discussion of the delay times

There is a critical path regarding the decision of fast and slow
cycles. The following times are relevant

Name	Time	Description
tas	30ns	Address setup time of the CPU (W65C816)
tpd	 7ns	Propagation Delay of Bank address latch (74F573)
tpd	 7ns	Propagation Delay of the decoding of /SLOW respectively /FAST
tpd	10ns	Propagation Delay of MUX (74F157)
tsu	 3ns	Setup Time of State Flip-Flops (74F74)
	----
Total	57ns

thus this logic limits the Fast Clock to 8.77MHz. In order to speed
up the logic the easiest is to put the decoding, state selection
and the flip-flops into a fast CPLD

Name	Time	Description
tas	30ns	Address setup time of the CPU (W65C816)
tpd	 7ns	Propagation Delay of Bank address latch (74F573)
tsu	 7ns	Setup Time of CPLD
	----
Total	44ns

this limits the Fast Clock to 11.36MHz.

The CPLD has the advantage to reduce the number of required chips and can
as well create other selection signals.

Or use a dedicated CPLD and integrate Flipflops

Name	Time	Description
tas	30ns	Address setup time of the CPU (W65C816)
tsu	 5ns	Setup Time of CPLD
	----
Total	35ns

which would support the full speed 14MHz Clock of the W65C816.