6502.org

Programmer by trade, so beware I don't really know what I'm talking about when
it comes to hardware.

The idea of making a Mini-ITX form factor SBC has been lurking in the back
of my head for a long time. Many variations have been considered, including
6502, 680x0 and ARM based ones. But after making a simple 6502 2MHz backplane
based computer (all through hole components), I decided to see what could be
done with the 65c816 CPU.
One of the reasons for choosing this particular CPU is that it is available,
even in modern packaging. I decided to take a "modern" approach, meaning SMD,
4 layer PCB.

After reading a lot of posts in the 6502.org forum I came up with the following
choice of components.

The CPU is of course the 65c816, the address and data
busses are made available via two 74ABT541, a 74ABT573 and a 74ABT245.

Instead of using (E)EPROM I decided to go with same flash this time, speed and
the potential for changing the contents in circuit made me choose the SST39SF040.

To make this a real computer a Real Time Clock is needed, DS1511 seems like a
nice fit.

Memory is provided by no less than 8 x 512K SRAM modules, fast small and
available in SOJ packages.

For storage a CF Card in True IDE mode has been chosen, mainly because it
is easy to connect to the system.

A real computer must have at least one RS232 interface, the SCC2692 was chosen for
it's ability to provide two of these interfaces in a nice package. It is
accompanied with two MAX3232 level shifters.

A printer/parallel port is also needed, a W65S22 provides just enough I/O to
more or less full fill the requirements to a printer port.

Additional I/O like PS/2 is provided by another W65S22.

A clock circuit is realized with a 14 DIL Oscillator, fed through a 74AC74. It
is my understanding that the 74AC74 will provide a compatible clock signal.

Finally all of this is glued together with an Altera MAX 7000 CPLD 5ns. These are
readily available 5V and comes with a free development environment. I have only
used old GALs with WinCUPL until now, but I hope the transition to this new
monster "GAL" will be educational but not to bumpy...

The observing reader will notice that real computers have some sort of VGA (or
better) output. Well that is what the expansion slot is for, since I don't know
how this will be solved yet (I have a couple of ideas...). Maybe the VGA will
be onboard in the next version.


Puzzles (for me at least):

I've seen some schematics with 74S1051/3 connected to the address and data
busses. I haven't really found a good explanation anywhere but I'm guessing it
is supposed prevent ringing/spikes?

Are all the relevant pull-up and series resistors in place, especially
connections to and from the CPLD?

Any input is greatly appreciated.

/norby

Any possibility of posting monochrome versions of your schematics? I'm not able to read part of them because apparently there is some light blue or green in there—it appears to me that there are missing connections.

That said, here is what I was able to glean:

• If you haven't already purchased parts, I recommend that you use the NXP26C92 DUART in place of the SCC2692. The former responds faster to chip selects, uses a bit less power, supports higher standard baud rates and most significantly, has 8-deep FIFOs on both the receivers and transmitters. Utilizing proper coding, the deeper FIFOs will assist in reducing the interrupt rate at high data rates. I have working code available if you are interested.
• While on the subject of the DUART, a 3.6864 MHz can oscillator is preferred to using a roll-you-own crystal oscillator. You will end up spending about the same amount of money on parts, but will use less board real estate and be guaranteed that the oscillator will be stable under all reasonable operating conditions.
• Again on the DUART, I discovered that simultaneously asserting (negating) both /RDN and /WRN apparently produces an undefined operation in the device, causing it to not connect to the data bus at all. The data sheet sort of implies that these inputs are mutually exclusive but doesn't really elaborate. Also, beware of the effects of 65C816 dead cycles (when the expression VDA || VPA is false, where || is logical OR) on the address bus when indexed addressing is used to select a DUART register.
• All 65xx I/O silicon must have chip selects and RWB valid before the rise of Ø2. It's not clear to me on your drawing, but it seems that RWB on the 65C22s is connected to something other than RWB on the 65C816. Such an arrangement will not work.
  
  Note that all other devices should also be selected as soon as the address bus becomes valid (that is, when the expression VDA || VPA is true), but should not be read- or write-enabled until the rise of Ø2.
• Unless there's a need for 3.3 volt operation, a single MAX-238 transceiver may be a better choice for your application than the two MAX-3232s. You'll consume less board real estate, use fewer charge pump capacitors and get stronger output drive. The MAX-238 uses four 1µF charge pump caps and one 1µF bypass cap. I use tantalums for that application, due to their small size. The MAX-238 is available as PDIP24 or SOIC24—I use the latter package in POC V1.1.
• I see a 74LS74 on one of the sheets? What's that device's purpose and why 74LS?

Here is a monochrome version of the schematics.

- I didn't know there was a better version of the 26C92 with FIFO and all - thanks for pointing that out.

- Regarding the oscillator, I was under the impression that a crystal + two capacitors is all that was needed, but I might be wrong.

- Regarding R/W I put that into my CPLD, and then hopefully it will come out as /WE about 5 ns later, is that going to much different from say a buffer?

- The single 74LS74 is for turning on the ATX power supply. I figured not much need for anything fancy

/norby

Nice work. If you are so inclined, check out my SBC-3. It used the low part of PHI2 to provide video data to a 256 color composite or s-video output. The XC95108 took care of the video timing, bank address latching, and chips selects.

You may also want to check out my 65SPI. This can be integrated into a larger CLPD to provide more decoding, etc. Having SPI opens up a lot of options for I/O. Easy Ethernet for one and possibly sound for another. My SPI-IDE/CF adapter works well for disk access too.

There are of course may options available and I won't feel offended if you do not use any of these. Sometimes its about the journey, not the destination.

Enjoy your journey!

Daryl

That arrangement does work. However, it reflects a time when integrated (can) oscillators were expensive. The thing with can oscillators is that you can always be sure that they will oscillate and that they will be on frequency (100 PPM is common).
Using the CPLD to generate a Ø2-qualified read- and write-enable signals is good and is what I'm going to be doing in POC V2. However, the RWB input on all 65xx peripheral devices has to be be valid before the rise of Ø2. Ergo the proper method is to connect all the RWB inputs on 65xx silicon to RWB on the 65C816.
As a Spanish speaking person might say, ¡No necesita! Carefully peruse the DS1511's data sheet. Hint: look at the Vbaux and /KS inputs, and the /PWR output. Everything you need for ATX-style soft power control is there. Page 17 of the data sheet elaborates:

• The DS1501/DS1511 incorporate a wakeup feature, which powers on at a predetermined day/date and time by activating the PWR output pin. Additionally, the kickstart feature allows the system to be powered up in response to a low-going transition on the KS pin, without operating voltage applied to the VCC pin. As a result, system power can be applied upon such events as key closure or a modem-ring-detect signal. To use either the wakeup or the kickstart features, the [DS1511] must have an auxiliary battery connected to the VBAUX pin, and the oscillator must be running.

Speaking of the DS1511, the /RST output should be pulled up to Vcc with a resistor but otherwise not connected to anything.

On the CPLD I see that the /GCLR input is not used. You might want to consider tying that to /RES so any flops and state machines you set up within the CPLD are reset to a known condition when the system is initially powered.

I also see RDY and RDY_OUT. What is RDY_OUT's purpose?
The programmable watchdog timer in the DS1511 has a 10ms resolution and is what I use for the jiffy IRQ in POC (POC's jiffy IRQ rate is 100 Hz)—no 65C22 needed. From that jiffy IRQ I am able to generate arbitrary length time delays and maintain a 32 bit system uptime counter. Timer functions are also available in the 26C92 and run at a submultiple of the 3.6864 MHz baud rate clock frequency.

The problem with using the 65C22's timer for jiffy IRQ generation is that the timer's operating rate is a submultiple of Ø2, which means if you change the Ø2 frequency, the jiffy IRQ rate likewise changes. Also, in some cases the Ø2 frequency may not be evenly divisible for the desired IRQ rate, which means a software clock driven by 65C22-generated IRQs will drift.
Garth's not just trying to drum up business. His 4MB DIMM will consume less space than eight SRAMs soldered to your mainboard, plus comes fully tested and ready for service. The more compact area of his DIMM will help to reduce bus loading, plus reduce the effort needed to lay out your board. Plus you won't be soldering 288 J-leads on a bunch of SOIC chips.
He would need four receivers and transmitters to support both of the DUART's channels.

/norby

I think I've read you pages a at least three times, they really helped me understand how 65xx system is supposed to work.

I actually have a I2C interface in the schematics, sheet 2 middle bottom. Heavily inspired by your pages.

The plan was actually to use the RTC to generate the OS timer interrupt e.g. 100Hz like BDD does, and then there is an additional timer T2 from a 6522 for other timing stuff, delays etc.

I like the idea of using memory modules, I'm just not so happy about the connector. I was actually looking into doing the same thing but with a SIMM-72 connector instead, but .... maybe next version...

The biggest problem with using MC14xxx is that as far as I can tell -12V is fading from ATX PSUs. I don't even think it is mandatory in the standard anymore.

I think I will just ditch the 74S1051/3, no point in messing with something I have no clue about.

/norby

Noted and changed in the schematic. The two 6522 are now connected directly to R/W, all other devices are connected to /WE from the CPLD.
I saw the potential for doing something clever with the DS1511 and power, but I wasn't sure how to do it. I find the datasheet a bit confusing.
If I understand the datasheet correctly I need a battery connected to VBAUX, in order to use the KS + PWR feature right?
One of the reasons for using the 1511 in the first place was that it didn't need an external coin battery.
But would it be possible to power the VBAUX with a simple voltage divider feed from the ATX PSUs +5V standby output?
All my /RES are tied together, and the DS1813 has an internal 5K5 pull to make sure it is high under normal circumstances.
I connected the DS1511's /RES too because I want to be able to use the watchdog feature of it. Since it is open drain I figured it was ok to do so?
That is why I want to use the RTC for the jiffy IRQ, and a T2 for other non critical timing.
Noted and fixed in the schematric, thanks.
I remember reading somewhere that if you wanted to use the RDY signal for whatever purpose (debugging, waitstates etc) you must put in a resistor or a diode.
I can't remember where I read it, but this is copied from the WDC65C816 development board schematic.
I would like to use it to possible insert waitstate and/or single step the CPU.

/norby

You can get it to a little better than two seconds a day (if the crystal were perfect), and if that's not good enough, you can make the software add or subtract a tick every so many. My HP-41cx calculator has that, although it has been accurate enough as it is, so I have not used that feature. Even if the crystal is not very accurate, it lets you get extremely accurate as long as the crystal frequency is consistent (aged and kept at a constant temperature).

I looked quickly at the RTC and saw the one-second resolution but I didn't catch the 100Hz interrupt output. That's the rate I have coming from T1 of VIA1 on mine.

What don't you like about the memory module's connector? It can be straight pins too, so the module goes parallel to the board it's plugged into, instead of at a right angle. You could conceivably also solder the pins right into the motherboard, with no socket. No signal line is more than .2" from an AC ground, and the pins are on .1" centers to make it friendly for standard perfboards. Daryl used it at 12MHz with three expansion cards, with no bus drivers, without issues.

I have no doubts that this works, and by all means I'm not a hardware guy, but to me it seems odd/strange to have a male connector on something like a memory module... maybe it brings back not so fond memories (no pun) of Amiga ZIP days....

/norby

Were those really weak? BDD was talking about some kind that was really thin. These however are the same thickness as the pins that the ribbon cable on IDE hard-disc drives plug into on a PC motherboard, much thicker than IC pins. The only thing you have to be careful of is that when you pull a module out of the socket, you pull it out straight so you don't bend the pins on one end. It would be possible to put the socket on the module and the pins on the motherboard (instead of vice-versa), although I'll have to figure out a way to test it-- maybe just solder a couple of pin headers tail to tail.

The +/- 12 volt outputs are mandatory in the ATX2.0 and ATX-EPS standards, so they will be around for a long time. Also, power supplies have to be backward compatible with older hardware to assure interchangeability. That said, the MAX-248 is still the most compact arrangement, even though the charge pump caps are required. I just finished a revised layout for my POC V2 unit, in which I replaced the two MAX-238 transceivers with a single MAX-248, the latter which comes in a PLCC44 package. The layout was simpler and tighter, plus I won't be soldering SOIC24 packages.
Unless you are designing something with long buses, the Schottky diode arrays are probably window dressing. They are used mostly on backplanes, where signal reflection problems can be onerous.
All Dallas Semiconductor data sheets are confusing. If you think the DS1511's data sheet is confusing, you ain't seen nothin' yet. The DS1216x series of smart-watch data sheets are worse. Dallas further confuses the issue by often mixing topics, leading one to believe that in order to implement wanted features, unwanted ones also have to be implemented. Fortunately, their products are far better than their data sheets.

Anyhow, to use /KS (push button input) and /DPWR to control the power supply, proceed as follows:

1. Create a voltage divider consisting of a 2.2K resistor in series with a 3.3K resistor.
2. Connect the free end of the 2.2K resistor to +5VSB on your power supply's main motherboard connector—that would be pin 9.
3. Connect the free end of the 3.3K resistor to ground.
4. Attach the junction of these resistors to Vbaux on the DS1511.
5. Connect /KS through a 3.3K resistor to Vbaux.
6. Connect /DPWR to PS_ON# on your power supply's main connector—either pin 14 (20 pin connector) or pin 16 (24 pin connector).
7. Connect one side of a push button to /KS. Connect the other side of the push button to ground.

I recommend that you bypass the push button with a 0.1µF capacitor to filter out any high frequency noise that finds its way into the circuit.
The internal pullup in the DS1813 is too weak to be relied upon. You should use an external 3.3K pullup on that circuit to guarantee that it doesn't get affected by noise.

As for the DS1511's /RST output, it doesn't respond to a push button the way the DS1813 does, so I question its value to you in this design. If you decide to use /RST, under what circumstances would you assert it? If you arrange for the watchdog to assert it, what about using the watchdog for jiffy IRQ generation? You can't do both.
You can drive RDY directly from the CPLD as long as you high-Z the CPLD output when not actively controlling RDY. The reason for the isolation has to do with the bi-directional nature of RDY. If the '816 executes a WAI instruction it pulls RDY low until the WAIting condition clears. Obviously you can't have RDY being constantly driven high, as WAI would effectively cause the '816 to sink an active output, eventually leading to some kind of failure.

In lieu of tri-stating the RDY output on the CPLD, you can isolate the circuit with a low-power Schottky diode, with the anode connected to the RDY pin on the '816. A pullup resistor is required no matter how you do it. Better to directly connect RDY to the CPLD and tri-state when inactive. That way you can use the CPLD to detect when a WAI is being executed.

The old SIPPs that were the mainstay of the minicomputer era and used in the Amiga used 0.018 inch round pins, which were indeed fragile. Your DIMM uses 0.025 inch pins, which while still vulnerable to fracture if bent more than a few times, are stronger. I concur with Norby that an edge connector, as used in modern DIMMs, would be more durable, although perhaps less hobby-friendly. If I were going to design my own memory module I'd arrange so it would plug into a PCI socket, which is both durable and compatible with high frequencies—standard PCI operates at 33 MHz.