6502.org

Hi guys

I've been writing a BBC Basic like 6502 assembler for windows and am a good way into that.
I'm now trying to implement optional instruction files something like this::

6502 instruction file [loaded by default]
6502 illegal instruction file
65C12 instruction file

Does anyone have a comprehensive and accurate list of 6502 illegal opcodes? I used to have a list myself, but for some reason I can't seem to locate it and google is coming up blank.

Many thanks!

Have a look at http://visual6502.org/wiki/index.php?ti ... 56_Opcodes and the links at http://visual6502.org/wiki/index.php?ti ... ed_Opcodes
cheers
Ed

I have some links to pages on them in one of the sections on my links page, at http://wilsonminesco.com/links.html#65fam .

Fantastic - thanks very much guys
I'll be posting an alpha video demo of my assembler soon. let me kn ow what you think?

I like Neil Parker's take on things ... very colorful and informative.

Mike

Might be worth noting that the 65C12 is like a 65C02 but without the TRB and TSB instructions (which are also[*] missing on the 65816) - it's a CPU found in Acorn's BBC Master computer. (Their external Second Processor used a 65C02, whereas the internal Coprocessor for the Master used a 65C102)

Edit: [*] as Mike points out below, this is not so!

I believe that TRB and TSB are there on the 816 (BBD will no doubt confirm). It's the BBR, BBS, RMB and SMB instructions that aren't there, probably because they suck up too much opcode space.

Mike

Silly me - you're quite right. So, the 65C12 lacks both sets.
Thanks for the correction
Ed

I don't miss them. Even when I did 65C02 development I never found a use for them. Their space was taken up by more useful instructions in the '816.

I have never used them either. It would be nice if they were there with an absolute (instead of ZP) addressing mode, to make them useful for I/O. I guess they were in ZP because a few microcontrollers had I/O there and they had so little ROM that it was important to save one byte each time one of these instructions was encountered; but that's not normal for our applications. The '816 of course has so many additional instructions and addressing modes that are more important, that keeping BBS & friends would have required using the WDM op code extension and making them 5-byte instructions taking probably 8 clocks. I probably should be always bank 0 (regardless of the data bank register) as that's where I/O would normally be.

TRB and TSB are very useful in I/O work,as they may be used on hardware registers to turn off or turn on features (but not on the NXP 2691, 2692 or 2698!). In the 65C816, TRB and TSB can process 16 bit values, making them extra useful in filesystem structure manipulations. For example, in UNIX-like filesystems, file characteristics are encoded into a 16 bit value, of which nine bits specify read, write and execute permissions for owner, group and others. Real easy to diddle with the '816 in 16 bit accumulator and memory mode and a 16 bit mask in the accumulator.

One of my reasons for ignoring BBR and BBS, other than their limitation to ZP addressing, is that the bit being tested is hard-coded into the instruction, making it a hassle to write a routine that can change which bit it's testing on the fly. Also, I mostly use bits 6 and 7 (or 14 and 15 if the m bit in the 65C816's status register is cleared) for flag purposes, which are easily tested with a BIT instruction. Or BIT immediate can be used...plus TRB and TSB can readily clear or set those bits. There's lots of bit-twiddling flexibility without the BBR and BBS instructions being present.

Yes, and I do use TSB, TRB, and BIT (with bits 6 & 7 having a privileged place), plus putting bit-bang clocks on ports' bit 0 to produce a full pulse on them with just two instructions INC DEC; but it would still be nice to be able to set or clear any arbitrary bit in a sigle instruction without affecting processor registers, or to be able to test and conditionally branch on any arbitrary bit (regardless of position in the port), all in one instruction.

PIC16 microcontrollers may appear to have an advantage there, but that advantage kind of disappears when you consider a couple of serious drawbacks. Without resorting to an inefficient mickey-mouse bank-switching scheme, they can only address 128 combined RAM and I/O and other special-function register addresses; and with bank-switching, you only get 512 total, in four banks. To make it worse, BTFSC (bit test file skip if clear) and BTFSS (bit test file skip if set) really only let you conditionally branch forward and around a single instruction; so if you need to branch around more, or branch backward, you have to use the opposite test and follow it with a GOTO to conditionally branch. It takes 8 to 12 clocks.

DEC and INC would blow up on my POC unit if applied to some of the 26C92's registers, as the R-M-W sequence would violate timing on the device with the MPU running any faster than a cheap pocket calculator. Ditto with TRB and TSB.

Aside from potential timing issues, I have fastidiously avoided using DEC and INC on hardware due to the non-obvious effects that such instructions can have. Way back when when I was first learning this stuff (c. 1970), we were schooled to never use R-M-W instructions on hardware, it being deemed bad programming practice that would bite you in the...er...gluteal region. I still think that way, which proves that I really am a big, dumb dinosaur.

I do use BBR/BBS and RMB/SMB instructions for I/O, and Garth is certainly correct about their aptness in that regard. My experiences have been 100% positive. To give the subject the attention it deserves, I've started a new thread: huge speedup with 65C02 I/O mapped into zero-page

cheers
Jeff