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1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Jan 26, 2014 8:34 pm
by ElEctric_EyE
First:
I'm using an ASUS MT276HE LCD flat panel display for my desktop computer and a
custom video hardware project.
The desktop computer outputs an HDMI signal into the HDMI-1 port of the monitor. I use this computer for Xilinx ISE14.1 and according to the monitor 'Information' on this input signal, the video board is outputting a 1920x1080 @60Hz.
The hardware project outputs a RGB signal to the monitor's RGB port. The monitor reports an input signal of 1920x1080 @50Hz.
For this monitor the recognized resolutions according to the owners manual are below. I initially focus on the last line for 1920 x 1080 @ 148.50MHz pixel clock...
Second:
The custom video board has an onboard 100MHz can oscillator. From this the PLL divides by 5 for 20MHz, then multiplies by 52 for 1040MHz. For the video generator portion, this 1040MHz is divided by 7 for 148.57MHz, very close to the spec. Then it is divided by 14 for cpu section & hardware circle/line/pixel plotter, which run @ 1/2 of 148.57MHz successfully interfacing to the external SyncRAM.
The cpu programs the Horizontal/Vertical Sync Generator with the following spec's:
Code: Select all
LDA #1920 ;2570 (2200 ideal for 67.5kHz) total H cycles @148.5MHz 17.306uS -> 57,782kHz
STA hVIDEO
LDA #25 ;55
STA hFRONT
LDA #550 ;550
STA hSYNC
LDA #75 ;95
STA hBACK
LDA #1080 ;1139 total @148.5MHz -> 1139 x 17.306uS = 20.09mS = 49.762Hz
STA vVIDEO
LDA #2 ;2
STA vFRONT
LDA #55 ;55
STA vSYNC
LDA #2 ;2
STA vBACK
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18SyncRAM board
Posted: Sun Jan 26, 2014 8:49 pm
by ElEctric_EyE
Simple software written for the 65Org16.b to draw the above pic. The Line/circle/pixel hardware generator puts the 65Org16.b in a ready state to halt the cpu when any last coordinate has been sent. The generator is outputting pixels to the SyncRAM during this time. No precautions are taken to avoid the snow effect, yet:
Code: Select all
START: LDA #$1000
TAZP ;SET ZEROPAGE @$1000_0000
LDA #$1001
TASP ;SET STACKPAGE @$1001_0000
LDA #1920 ;2570 (2200 ideal for 67.5kHz) total H cycles @148.5MHz 17.306uS -> 57,782kHz
STA hVIDEO
LDA #25 ;55
STA hFRONT
LDA #550 ;550
STA hSYNC
LDA #75 ;95
STA hBACK
LDA #1080 ;1139 total @148.5MHz -> 1139 x 17.306uS = 20.09mS = 49.762Hz
STA vVIDEO
LDA #2 ;2
STA vFRONT
LDA #55 ;55
STA vSYNC
LDA #2 ;2
STA vBACK
LDX #$0 ;black pixels
LDA CLUT,X
STA color
LDA #1920/2 ;fill top left quadrant black
STA fXlen
LDA #1080/2
STA fYlen
LDA #0
STA fXs
STA fYs ;FILL!
LDA #1920/2 ;fill bottom right quadrant black
STA fXlen
LDA #1080/2
STA fYlen
LDA #1920/2
STA fXs
LDA #1080/2
STA fYs ;FILL!
LDX #2
LDA CLUT,X
STA color
LDA #101 ;PLOT SINGLE red PIXEL
STA Xp
STA Yp ;PLOT!
LDX #6 ;blue pixels
LDA CLUT,X
STA color
LDA #300
STA fXlen
LDA #0
STA fYlen
LDA #319
STA fXs
LDA #239
STA fYs ;FILL! (test, thin blue fill)
LDA #0
STA fXlen
LDA #300
STA fYlen
LDA #319
STA fXs
LDA #239
STA fYs ;FILL! (test, thin blue fill)
LDX #2 ;red pixels
LDA CLUT,X
STA color
LDA #179
STA fXlen
LDA #179
STA fYlen
LDA #320
STA fXs
LDA #240
STA fYs ;FILL! (test, red rectangle)
LDX #$05 ;green pixels
LDA CLUT,X
STA color
;border
LDA #0
STA lx0
LDA #0
STA ly0
LDA #1919
STA lx1
LDA #0
STA ly1 ;DRAW LINE!
LDA #1919
STA lx0
LDA #0
STA ly0
LDA #1919
STA lx1
LDA #1079
STA ly1 ;DRAW LINE!
LDA #1919
STA lx0
LDA #1079
STA ly0
LDA #0
STA lx1
LDA #1079
STA ly1 ;DRAW LINE!
LDA #0
STA lx0
LDA #1079
STA ly0
LDA #0
STA lx1
LDA #0
STA ly1 ;DRAW LINE!
LDA #0
STA lx0
LDA #0
STA ly0
LDA #1919
STA lx1
LDA #1079
STA ly1 ;DRAW LINE!
LDA #0
STA lx0
LDA #1079
STA ly0
LDA #1919
STA lx1
LDA #0
STA ly1 ;DRAW LINE!
;SQUARE1
LDA #300
STA lx0
LDA #400
STA ly0
LDA #350
STA lx1
LDA #400
STA ly1 ;DRAW LINE!
LDA #350
STA lx0
LDA #400
STA ly0
LDA #350
STA lx1
LDA #450
STA ly1 ;DRAW LINE!
LDA #350
STA lx0
LDA #450
STA ly0
LDA #300
STA lx1
LDA #450
STA ly1 ;DRAW LINE!
LDA #300
STA lx0
LDA #450
STA ly0
LDA #300
STA lx1
LDA #400
STA ly1 ;DRAW LINE!
;SQUARE2
LDA #325
STA lx0
LDA #375
STA ly0
LDA #375
STA lx1
LDA #375
STA ly1 ;DRAW LINE!
LDA #375
STA lx0
LDA #375
STA ly0
LDA #375
STA lx1
LDA #425
STA ly1 ;DRAW LINE!
LDA #375
STA lx0
LDA #425
STA ly0
LDA #325
STA lx1
LDA #425
STA ly1 ;DRAW LINE!
LDA #325
STA lx0
LDA #425
STA ly0
LDA #325
STA lx1
LDA #375
STA ly1 ;DRAW LINE!
;4 interconnecting lines to join 2 squares for 3-D cube
LDA #300
STA lx0
LDA #400
STA ly0
LDA #325
STA lx1
LDA #375
STA ly1 ;DRAW LINE!
LDA #350
STA lx0
LDA #400
STA ly0
LDA #375
STA lx1
LDA #375
STA ly1 ;DRAW LINE!
LDA #350
STA lx0
LDA #450
STA ly0
LDA #375
STA lx1
LDA #425
STA ly1 ;DRAW LINE!
LDA #300
STA lx0
LDA #450
STA ly0
LDA #325
STA lx1
LDA #425
STA ly1 ;DRAW LINE!
LDX #7 ;plot yellow circle in top left Quadrant
LDA CLUT,X
STA color
LDA #320
STA xc
LDA #239
STA yc
LDA #180
STA ra ;DRAW CIRCLE!
;----------------------------------------------------------------------------------
LDX #6 ;plot blue circle in bottom right quadrant
LDA CLUT,X
STA color
LDA #1500
STA xc
LDA #850
STA yc
LDA #179
STA ra ;DRAW CIRCLE!
LDX #1 ;draw white lines from center of last circle
LDA CLUT,X
STA color
LDY #850 + 180
LRUN LDA #1500
STA lx0
LDA #850
STA ly0
LDA #1500 + 180
STA lx1
STY ly1
DEY
DEY
CPY #850 - 180
BPL LRUN
ENDALL JMP ENDALL
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Jan 26, 2014 9:05 pm
by barrym95838
Nice work! The 65Org16.b sure looks like a nice host (natural fit) for the stuff you're doing here.
Mike
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Mon Jan 27, 2014 12:31 pm
by ElEctric_EyE
Thanks Mike. There's a few issues to be resolved yet, but I posted not only to show it's possible for a home brew system to go HD, but because I've a question: When I try to match the pixel, horizontal and vertical frequencies to what is spec'd in the monitor's User Guide (which I posted above), the picture does not fit. Interestingly too, 1920x1080 @50Hz is not one of the reported modes in the guide, but the monitor still recognizes it.
EDIT: Also an interesting note. At this fine resolution, a radar sweep of a line drawing algorithm is useful as a fill for a circle for example. In the above pic, on the bottom right, I stepped the line drawing by 2 so one can see the interesting patterns.
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18SyncRAM board
Posted: Tue Jan 28, 2014 6:56 pm
by ElEctric_EyE
I forgot there was a problem with dx vs. dy in my line generator module. It cannot draw a diagonal line across the entire screen yet (although it seemed to work fine in 1024x768), so I had to add 2 software code to add 2 more lines to complete the diagonals. I also had to add 1 to the error accumulator in the line generator.
Also, I had to make a small change to the display module so the SyncRAM output is sync'd with the HV sync module, a delay of 2 cycles was needed. Now almost everything is good, except the random (white and red ) pixels which I suspect is a timing issue.
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Wed Jan 29, 2014 4:44 pm
by ElEctric_EyE
Now I have 4 PVB's outputting the same video.
With the pixels so small and each board adding noise in the form of maybe a 1/4 pixel, it becomes obvious now that this noise is going to be the enemy at this high resolution. I'll add in all the .1uF bypass caps on every board now and report back.
Here's a pic. Still extraneous data being written to the SyncRAM which is most visible in the bottom right. The noise I speak of is most noticeable in the red triangle. It almost appears solid red. Hopefully bypass caps will fix this.
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Tue Feb 04, 2014 7:49 pm
by ElEctric_EyE
The extraneous pixel problem has been fixed. It was a hardware timing problem with the SyncRAM R/W signal, it was late by one cycle. The hunt for the problem revealed to me that I could remove a state from the line plotter as well. This is a full cycle, so it effectively doubles the plotting time of the hardware state machine....
Strange that it only reared it's head when I plotted consecutive lines:
Code: Select all
LDX #2 ;draw red lines from center of last circle to the left
LDA CLUT,X
STA color
LDY #850 + 179
LRUN2 LDA #1500
STA lx0
LDA #850
STA ly0
LDA #1500 - 179
STA lx1
STY ly1 ;DRAW!
DEY
DEY
CPY #850 - 179
BNE LRUN2
I can do the following no problem to remove a delay I thought was needed:
Code: Select all
LDX #2 ;draw red lines from center of last circle to the left
LDA CLUT,X
STA color
LDY #850 + 179
LDA #1500
STA lx0
LDA #850
STA ly0
LDA #1500 - 179
STA lx1
LRUN2 STY ly1 ;DRAW!
DEY
DEY
CPY #850 - 179
BNE LRUN2
Tomorrow
I add the bypass cap's (really?!, yes really). Then finish code for a hardware copy/paste.
EDIT: I forgot to mention, the video timings are much closer to the monitor spec, and it sync'd right up and auto adjusted the incoming video. Each pixel is square with no blurriness.
Code: Select all
LDA #1920 ;2430 (2200 ideal for 67.5kHz) total H cycles @148.5MHz 16.363uS -> 61.111kHz
STA hVIDEO
LDA #205 ;205
STA hFRONT
LDA #50 ;50
STA hSYNC
LDA #255 ;255
STA hBACK
LDA #1080 ;1139 total @148.5MHz -> 1139 x 16.363uS = 18.638mS = 53.654Hz
STA vVIDEO
LDA #2 ;2
STA vFRONT
LDA #55 ;55
STA vSYNC
LDA #2 ;2
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Wed Feb 12, 2014 1:48 pm
by ElEctric_EyE
Got the copy/paste working, but reading the SyncRAM was only successful at 1/4 speed of the pixel clock, i.e. ~37MHz. It is a state machine that does back-to-back Read/Writes, 2 cycles per operation. 1 cycle to set up the address first, the second cycle to read or write the data as according to the data sheet.
If a write is successful at 74MHz and not a read, I suspect the FPGA data-in lines need to be delayed by an amount less than 1 cycle. I will have to investigate on delaying the IOBs on the FPGA.
In this pic, the upper left has a white triangle which was done by a single step radar sweep of the line generator. (The other triangles are double stepped). An upper portion of that is copied/pasted to another region of the screen. The second 50x50 pixel copy/paste is from the center of the upper left circle. It has been copied to the bottom right of the screen.
The purple circle fill is not successful by plotting concentric circles of decreasing radii...
As far as what is next in 1920x1080 mode, I think a hardware text plotter is in order after I get the Read/Write working @ 74MHz.
I don't think sprites will be possible as 98% of the RAM is used for the screen. However, 1 more mode is possible with 2 FPGA PROMs available. That will be in another thread later.
Here is the simple 65Org16 code for the 2nd copy/paste:
Code: Select all
LDA #50
STA bXlen
STA bYlen
LDA #300
STA bXc
LDA #210
STA bYc
LDA #1200
STA bXp
LDA #850
STA bYp ;BLIT!
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Mon Feb 17, 2014 12:42 am
by ElEctric_EyE
...I suspect the FPGA data-in lines need to be delayed by an amount less than 1 cycle. I will have to investigate on delaying the IOBs on the FPGA....
That was brought up
here. I have gotten the CoreGen tools to make one in Verilog, like I believe Arlet had done in that thread. I just wasn't up to his par at that time in my development, so I wasn't able to pursue his ideas.
It's not as simple as I thought it would be either. It will require another module, I will get into it very soon on a new thread.
I was off experimenting yesterday and today making a line scroll left to right then left again. Since the hardware line plotter only looks for the last 1 of 4 coordinates to start it's job, I thought I would post some simple code.
I got tired of the 'snow effect' real quick, so I sent the VSYNC signal into the 65Org16 as 1 of the control flags so the cpu only sends a plot command during a non-active vsync, so no tearing effect like if I would've send the command during a non-active hsync. (Also, as stated before, the cpu is halted by RDY when the hardware plotter is outputting data to the SyncRAM)
It's pretty cool, nice and short. I will have to make a video, it's very fast (the 'delay' code is at the bottom):
Code: Select all
LDA #%00000000000000000 ;16-bit 565 RGB
STA color
LDA #1919 ;clearscreen
STA fXlen
LDA #1080
STA fYlen
LDA #0
STA fXs
STA fYs ;FILL!
BSCRX LDY #100
SCRX LDA #%1111111111111111 ;draw white lines
STA color
LDA #100
STA ly0
STY lx0
STY lx1
BCF1C $FFFE ;Branch if Control Flag 1 is Clear (0), CF1 is VSYNC input, so branch to itself and wait until vsync = 1, a non display period
LDA #200
STA ly1 ;DRAW LINE!
JSR DELAY
LDX #%0000000000000000
STX color
BCF1C $FFFE ;branch to itself. Wait till vsync = 1, non display period
STA ly1 ;CLEAR LINE!
INY ;inc horizontal position
CPY #500
BNE SCRX
LDY #500
SCRX2 LDA #%1111111111111111 ;draw white lines
STA color
LDA #100
STA ly0
STY lx0
STY lx1
BCF1C $FFFE ;branch to itself. Wait till vsync = 1, non display period
LDA #200
STA ly1 ;DRAW LINE!
JSR DELAY
LDX #%0000000000000000
STX color
BCF1C $FFFE ;branch to itself. Wait till vsync = 1, non display period
STA ly1 ;CLEAR LINE!
DEY ;dec horizontal position
CPY #100
BNE SCRX2
JMP BSCRX
Delay:
Code: Select all
DELAY LDX #$001
LXI LDWi $00FF
GHI DEW
BNE GHI
DEX
BNE LXI
RTS
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Mon Feb 17, 2014 11:11 pm
by ElEctric_EyE
I was scrolling a circle yesterday, which is about 8x more cycles than a line and it plots fine on a vsync enable. I itch for animation, but I cannot pursue it yet. I must pursue the hardware first.
Today I made the registers readable by the cpu, which allows for e.g. INC/DEC on a circle radius, which is the last register to be written that auto starts the hardware generator for a circle. Same applies for line, fill, etc.
Also, in 1 day I surprised myself by also attaching a character ROM to the vga module and almost had immediate success with the hardware bitmap plotter. This is due to the fact of learning Verilog and also what the SyncRAM needs. Also, I've done character plotting in 6502 software: Shift left, test, plot or clear. Verilog is awesome! Same concept but I made a hardware machine, which is functioning at 35MHz.
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Tue Feb 18, 2014 11:25 pm
by ElEctric_EyE
I continued progress on the Verilog for the hardware character plotting machine. I refined the logic for 8x8 characters of 2 fonts, DOS & C64. Since these are 8-bit fonts I was able to pack them into the 1Kx16 CharROM side by side.
The display logic chooses either based on an Attribute bit [8], while the character data itself is present in bits [7:0] of the Attribute register. Bits [15:9] are unused at this point.
Also added a programmable background color variable, not assumed to be 16'h0000 anymore.
Working on programmable sizes for the character fonts currently. I've had success with individual sizes spec'd in Verilog using 'parameter' during experimentation phase.
Recently I've made alot more registers for software control replacing the parameter spec's. The project is growing (unfortunately)...
I have my eye on 2 variables the ISE14.1 is reporting on regarding the project, because they are headed towards max'ing out the Spartan6 according to the Verilog code I am adding:
Code: Select all
Number of Slice LUTs
3,920
5,720
68%
Code: Select all
Number of occupied Slices
1,232
1,430
86%
Tomorrow, hopefully I can finalize the variable size character plotting.
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Wed Feb 19, 2014 3:16 am
by player55328
What you are doing is pretty cool! You mentioned sprites earlier, I would think you would need at least 1 sprite for a hardware mouse pointer. Maybe instead of accessing memory for it have some registers for it's bitmap or a small rom to be able to select different kinds, pointer, hourglass etc. Keep up the good work, I share your enthusiasm for Verilog...
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Wed Feb 19, 2014 10:30 pm
by ElEctric_EyE
Thanks Ken!
I almost broke the machine. I decided to stop progress for today and save. I should've saved my first success...
I had success with 128x128, 64x64, 32x32, 16x16, but the original 8x8 I have a problem melding with the current logic. I'll work on it, also a left/right alignment issue...
The camera cooperated with me today for a close-up of pixels, looks like some noise maybe, not visible to the naked eye.
You're idea of a pointer, like for use with a hardware mouse pointer, shouldn't be too difficult using the blockRAM.
Currently, I'm saving the blockRAM for use when I have a hardware ellipse plotter. Then the vector line drawing and real 3d animation begins.
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Wed Feb 19, 2014 11:58 pm
by ElEctric_EyE
Some of the device usage seems to have gone down:
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Mon Feb 24, 2014 11:50 pm
by ElEctric_EyE
Alright!
Got several problems fixed now on 1 PVB.
Today I fixed the Verilog character plot code so it will plot 5 different sizes, x & y the same. Not too interested in using up even more resources for different x's & y's (i.e. 16x8, I pursued it for awhile).
So the character plotter can now plot 8x8, 16x16, 32x32, 64x64 and 128x128.
Also, I was able to increase the speed of the part of the module which plots circles/lines/fill/blit/plot pixel to 74MHz. Major success!
Camera not as cooperative as the other day.
Char plotter plots characters of different sizes/colors/background colors.
Blit copies and pastes to a different portion of the screen.
White circle of radius 200 scrolls left to right.
Snapshot!