6502.org

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module SPI(
  input  clk,
  output pin_clk,
  output reg pin_MOSI,
  input  pin_MISO,
  input  [7:0] mosi,
  output [7:0] miso,
  input  write,         // 1 means start transfer
  output ready,         // 1 means byte ready on miso
  input  slow
);
reg pin_in;
//                   v_bbb_C_ccccccc
reg [11:0] cnt = 12'b1_000_0_0000000; //  
assign pin_clk = cnt[7];   // SPI clock
assign ready =   cnt[11];  // after 8 bits shifted goes high

reg [7:0] data = 8'b00000000;
assign miso = data;
wire [11:0] next;
assign next = cnt + 64; //(slow ? 1 : 64);
always @(posedge clk) begin
  pin_in <= pin_MISO;
  if(write) begin   // trigger on completed = start!
    data <= mosi;                   // load data for output
    cnt  <= 12'b0000_0000_0000;      // 
  end

  if(ready)
    pin_MOSI <= 1'b1;
  else begin
    cnt <= next;
    if((cnt[7]==0)&&(next[7]==1)) begin   // UP transition
      pin_MOSI <= data[7];
      data     <= {data[6:0],pin_in};
    end
  end

end
endmodule

Code: Select all

SPI_DATA        equ   IO_PAGE + $10
SPI_CTL         equ   IO_PAGE + $11