65c02 Emulator
Posted: Tue Mar 02, 2004 9:31 pm
Greetings,
I have been working on a general purpose 65xx simulator program these past few weeks. I'm wanting to share it with people but everyone I post seems no one cares (except me).
The CPU Core is designed to be a CPU object that is a self-contained blackbox that can be used anywhere. This means that it uses events to communicate with the outside world.
I have implemented a 65c02 core, 6502 core, will be implementing a 6502u (6502 with undocumented opcodes), 65816, and a never released 65832 (32-bit 65816 decendant) (just for the heck of it since I have the data sheets).
The simulator will use the core for single stepping and debugging. The simulator will have an interface to plugin assembler, dissambler interfaces. Ultimately, given an assembly language file, I can change the source codes while in debug mode and won't have to restart or recompile to get the changes, just step into the next line. This is important, because I make most my NES/SNES/ATARI games in ASM anyway as opposed to some other language... ?C?, ?Pascal?.
The memory object sends events if a memory location has changed/been read. Basically you can watch all memory or just a specified range. If the range changes, you can be notified (and update a graphics display or whatever).
In recent days, I've started moving this project into C++ (it was in C# originally) because of the optimizer. Now, if you are using the optimizing module, when a JSR is invoked, it'll scan from the target range to the RTS and then will compile it into native code (in this case, Intel x86). Each subsequent call it'll just execute the native code instead. If a memory location in that range changes, it'll recompile that range. If a branch causes a jump outside the range then the compiled code will execute until the branch and then it'll execute the branched location emulated. If it returns into the range, it'll just run emulated (I can't compile everything and all things potentially dynamic).
This optimization isn't important so much for the 8-bit CPU, but becomes more important for the 16-bit version. I'm still trying to work out the timing in the CPU core, but even more so, I have to work out the timing as well in the compiled code, it still has to know the clock cycles and keep timing for it. Sigh.
Anyway, that's the project. I'm not such a low-level programmer usually, usually I write business applications for a living. But this is fun.
Anyway, is anyone here interested in using it when it's ready? I'll have the first 65c02 CPU core ready within the month and then the simulator program comes after I implement the assembler. I've never written one so this will be my first assembler.
Thanks,
Leabre
I have been working on a general purpose 65xx simulator program these past few weeks. I'm wanting to share it with people but everyone I post seems no one cares (except me).
The CPU Core is designed to be a CPU object that is a self-contained blackbox that can be used anywhere. This means that it uses events to communicate with the outside world.
I have implemented a 65c02 core, 6502 core, will be implementing a 6502u (6502 with undocumented opcodes), 65816, and a never released 65832 (32-bit 65816 decendant) (just for the heck of it since I have the data sheets).
The simulator will use the core for single stepping and debugging. The simulator will have an interface to plugin assembler, dissambler interfaces. Ultimately, given an assembly language file, I can change the source codes while in debug mode and won't have to restart or recompile to get the changes, just step into the next line. This is important, because I make most my NES/SNES/ATARI games in ASM anyway as opposed to some other language... ?C?, ?Pascal?.
The memory object sends events if a memory location has changed/been read. Basically you can watch all memory or just a specified range. If the range changes, you can be notified (and update a graphics display or whatever).
In recent days, I've started moving this project into C++ (it was in C# originally) because of the optimizer. Now, if you are using the optimizing module, when a JSR is invoked, it'll scan from the target range to the RTS and then will compile it into native code (in this case, Intel x86). Each subsequent call it'll just execute the native code instead. If a memory location in that range changes, it'll recompile that range. If a branch causes a jump outside the range then the compiled code will execute until the branch and then it'll execute the branched location emulated. If it returns into the range, it'll just run emulated (I can't compile everything and all things potentially dynamic).
This optimization isn't important so much for the 8-bit CPU, but becomes more important for the 16-bit version. I'm still trying to work out the timing in the CPU core, but even more so, I have to work out the timing as well in the compiled code, it still has to know the clock cycles and keep timing for it. Sigh.
Anyway, that's the project. I'm not such a low-level programmer usually, usually I write business applications for a living. But this is fun.
Anyway, is anyone here interested in using it when it's ready? I'll have the first 65c02 CPU core ready within the month and then the simulator program comes after I implement the assembler. I've never written one so this will be my first assembler.
Thanks,
Leabre