6502.org

For someone who wants to program, and not to solder, as far as I can tell, there's only one way to buy a new 65816-based system - the educational kits from apatco:

There is a $200 kit available:
http://www.apatco.com/shop/index.php?productID=674
Also available assembled, but even more pricey at $300:
http://www.apatco.com/shop/index.php?productID=685

It is also possible to buy 65816 chips, and several people have done their own systems designs, and done small upgrade boards for 6502-based systems. But I don't believe any of those are for sale.

John Kortink sells a BBC second processor board with a 65816 option, but only as an upgrade (it needs the Tube chip from an original "cheese wedge")

The only other approaches I can think of to get a physical 65816 system to program on, without soldering, are to buy a secondhand apple ii gs or a SNES. The SNES is probably fairly easy to get hold of, but would need further equipment to develop for.

Have I missed any small-scale sellers of built systems?

For EUR80 or $120 you can buy a development system for the SNES cartridge port:

https://www.assembla.com/wiki/show/quickdev16#order

I have much less invested in POC V1 if you don't count the dumb serial terminal I use for I/O (could easily be a PC). Not sure, though, how useful POC V1 would be to someone getting their feet wet with the '816.

I agree, it does seem a little pricey perhaps. Hard to say. The baffling thing is that they don't bother to tell you what you get for your money. In other words, no specifications! Speed? Memory? I/O? Not listed! [Edit: My mistake -- there is info listed. I overlooked the links in the left sidebar]

I see there's an LCD, which is nice... [128x64 pixel]

On the other hand, if you allow for inflation then their assembled unit is about half what I paid for my KIM-1. And a 65c816 is "slightly" preferable to a 1 MHz NMOS 6502!

Jeff

Re: specifications, I emailed Apatco and got a prompt reply.

I fail to see how they can claim 20 MHz operation when the glue logic is 74LS.

I will be offering a bulk buy for my SBC-4 later this year. It will be in kit form. For those who desire a little help, I might be able to solder some/all of the parts at additional cost.

Stay tuned to the SBC section of this forum.

Daryl

Great offer, thanks Daryl!

At least we know Daryl's stuff will perform.

BDD, if you mean Apatco's claim of 20 MHz operation, I confess that I'm somewhat skeptical as well.

By email they informed me, "FYI, the 20Mhz operation can be done by disabling the glue logic and creating your own." Sounds kind of extreme, to me. Would anyone actually do that? Even if you did, you'd probably also need faster memory & IO chips (or else Wait-State circuitry).

Personally I think a better plan would be to simply upgrade the existing glue logic with 74AC series or something similar. Limit the mods to adding a few series termination resistors on the strobe lines maybe. And settle for whatever speedup you can get, without expending a lot of effort.

The kit ships with both a 2Mhz and a 6Mhz crystal. I bet the boards perform just fine at such speeds -- and can probably be made to go even faster. But the 20 MHz figure seem awfully optimistic. I wonder if they have a demo system to back up the claim.

-- Jeff

http://www.apatco.com/forums/index.php? ... st__p__301

Just to clarify. The NCS EB50 was designed to be as flexable as possible as a base system to develop in an educational environment. It was also designed as an upgrade path to the NCS 2056T breadboard computer system. Because the 2056T uses the 74 series logic, the EB50 by default uses this logic as well. The current configuration limit, which is actaully the EEPROM which is 150ns, limits it's operation to 6.66Mhz hence the 6Mhz cyrstal that it comes with.

As some users may want to experiment with a faster system, the board has jumpers (JP1, JP2) which will reroute the CE signals for RAM, ROM chips to the J1 50 pin memory bus connector. As well, the JP3, JP4, & JP5 will reroute the U2, U3, and U7 to the J1 50 pin connector as well. This allows you to develop your own logic, maybe with CPLD or what ever.

The board runs extremely well, and was designed with simplicity in mind. The skies the limit for experimenting with the EB50.

It also will use the ViaUSB adapter from WDC and allows programming with the TIDE programming environment.

http://www.apatco.com/shop/index.php?productID=699

If you have any other questions or concerns, don't hesitate to contact us.

APATCO Technologies

No, if the EERPOM really takes 150ns to dish up the data, then it's too slow for a 6502 system at 6.66MHz. The memory would have to be faster. Yes, one period at 6.66MHz is 150ns, but from there you subtract the specified address setup time (tADS, 30ns for a 14MHz 6502) and the read data setup time (tDSR, 10ns for a 14MHz 6502) and probably some address-decoding logic time (I haven't seen your circuit), leaving you with about 100ns for the ROM at 6.66MHz. If you're running it at 3.3V, the spec.s say you need to take off another 15ns, leaving you with EEPROM that can dish up the data in 85ns @3.3V. In some systems (notoriously the Apple II), two memory accesses were done in each cycle, so even at 1MHz, you had to take the setup times and glue-logic times off of 500ns, not 1000ns. Fortunately the actual times are usually somewhat better than specified; but you can't plan on it.

Hi Garth,

Yes you are correct, that is why the Crystal is 6Mhz and not 6.6Mhz... 6.66 is the Theoretical limit with the EEPROM at 150ns. (1,000,000,000 / 150)

1/(6MHz) is 167ns per cycle. With setup times, that's still not enough time for a 150ns EEPROM unless the parts are significantly faster than they are specified to be. If you want reliability, 150ns is definitely not fast enough for a 6MHz system. It may work now, just by luck, and then a customer who operates it in a hotter environment and has a slightly lower power supply voltage (but still within spec) will have it not work and may not know why.

You're counting on the processor putting the next address out on the address bus the instant the phase 2 clock falls, and that is simply not the case. There is some processing that has to take place before it can get the address out there. You're also counting on the processor being able to wait for the next fall of the phase-2 clock to read the data; but it cannot wait that long. It needs it before that. That's what the setup times are about. Then if you have address-decoding logic that adds further delays that cut down the amount of time that the EEPROM can be allowed to have. That's why the timing diagrams are in the data sheet.